Dynamic register with low clock rate testing capability

A method for refreshing a dynamic register, the dynamic register comprising a first transmission gate and a second transmission gate operating in accordance with complementary clock signals, a first inverter disposed between the first and second transmission gates, a second inverter disposed at the output of the second transmission gate, the first inverter having a first input terminal and a first output terminal, the second inverter having a second input terminal and a second output terminal, the method comprising the operations of:

• (a) coupling a feedback path from the first output terminal to the first input terminal to create a first static loop;
• (b) coupling a feedback path from the second output terminal to the second input terminal to create a second static loop;
• (c) providing a control signal separate from the complementary clock signal to the first and second static loops;
• and
• (d) activating the first and second static loops via the control signal to refresh the dynamic register;
• wherein operation (a) comprises:
• coupling a first transistor to the first output terminal of the first inverter;
• coupling a second transistor to the first input terminal of the first inverter;
• coupling an input of a first loop inverter to the first transistor and an output of the first loop inverter to the second transistor;
• coupling gate terminals of the first and second transistors to the control signal;
• coupling a third transistor to the second output terminal of the second inverter;
• coupling a fourth transistor to the second input terminal of the second inverter;
• coupling an input of a second loop inverter to the third transistor and an output of the second loop inverter to the fourth transistor;
• and
• coupling sate terminals of the third and fourth transistors to the control signal.

A system for refreshing a dynamic register, the dynamic register comprising a first transmission gate and a second transmission gate operating in accordance with complementary clock signals, a first inverter disposed between the first and second transmission gates, a second inverter disposed at the output of the second transmission gate, the first inverter having a first input terminal and a first output terminal, the second inverter having a second input terminal and a second output terminal, the system comprising:

• (a) a first static loop coupled to the first inverter as a feedback path from the first output terminal to the first input terminal, the first static loop receiving a control signal, the first static loop being activated or deactivated by the control signal, the first static loop refreshing the first inverter when activated;
• and
• (b) a second static loop coupled to the second inverter as a feedback path from the second output terminal to the second input terminal, the second static loop receiving a control signal, the second static loop being activated or deactivated by the control signal, the second static loop refreshing the second inverter when activated;
• wherein the first static loop comprises:
• a first transistor coupled to the first output terminal of the first inverter, a gate terminal of the first transistor being coupled to the control signal;
• a second transistor coupled to the first input terminal of the first inverter, a gate terminal of the second transistor being coupled to the control signal;
• and
• a first loop inverter having an input coupled to the first transistor and an output coupled to the second transistor;
• and wherein the second static loop comprises:
• a third transistor coupled to the second output terminal of the second inverter, a gate terminal of the third transistor being coupled to the control signal;
• a fourth transistor coupled to the second input terminal of the second inverter, a gate terminal of the fourth transistor being coupled to the control signal;
• and
• a second loop inverter having an input coupled to the third transistor and an output coupled to the fourth transistor.

A method for refreshing data in a system having a dynamic circuit element, the dynamic circuit element having an input terminal and an output terminal, and a static loop that forms feedback path from the output terminal to the input terminal, the method comprising:

• (a) coupling the static loop to the dynamic circuit element;
• (b) clocking the dynamic circuit element using clocking signals;
• and
• (c) refreshing the dynamic circuit element via the static loop using a control signal;
• wherein operation (a) comprises:
• coupling a first transistor to the output terminal of the dynamic circuit element;
• coupling a second transistor to the input terminal of the dynamic circuit element;
• coupling an input of a loop inverter to the first transistor and an output of the loop inverter to the second transistor;
• and
• coupling gate terminals of the first and second transistors to the control signal.