Microcomputer and microprocessor having flash memory operable from single external power supply

A semiconductor integrated circuit comprising:

• a memory array including:
• first electrically erasable and programmable memory cells, and
• second electrically erasable and programmable memory cells which store information;
• a register capable of storing the information therein;
• and
• a peripheral circuit which is coupled to the memory array and which controls a read operation, an erase operation or a programming operation for the memory array, wherein the peripheral circuit is further coupled to the register,
• wherein the information stored in the second electrically erasable and programmable non-volatile memory elements is read out to the register in response to an initialization operation of the semiconductor integrated circuit, so that characteristics of the peripheral circuit can be controlled based upon the information stored in the register.

A semiconductor integrated circuit, comprising:

• electrically erasable and programmable non-volatile memory elements that store information;
• a register capable of storing the information therein;
• and
• an internal circuit coupled to the register,
• wherein the information is transferred from the electrically erasable and programmable non-volatile memory elements to the register in response to an initialization operation of the semiconductor integrated circuit, so that characteristics of the internal circuit can be controlled by the information stored in the register, wherein said information comprises trimming data.

A semiconductor integrated circuit comprising:

• first memory cells;
• second memory cells which are electrically erasable and programmable non-volatile memory cells and which store information therein;
• a register capable of storing the information therein;
• and
• a peripheral circuit which is coupled to the first memory cells and which controls a read operation or a write operation for the first memory cells, wherein the peripheral circuit is further coupled to the register,
• wherein the information in the second memory cells is read out to the register in response to an initialization operation of the semiconductor integrated circuit, so that characteristics of the peripheral circuit can be controlled based upon the information in the register.