Nonvolatile flash memory device usable as boot-up memory in a digital information processing system and method of operating the same

A flash memory device comprising:

• a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns;
• a power detecting circuit to generate a first detection signal when a power supply voltage is lower than a predetermined detection voltage;
• address generating means for internally generating an address in response to the first detection signal;
• a read circuit to read data from the memory cell array dependent on internally generated addresses of the address generating means;
• and
• a control circuit to generate a control signal to control the read circuit dependent on device information and whether or not the power supply voltage is lower than a predetermined detection voltage;
• wherein the read circuit comprises:
• a row selecting circuit to select one or more rows of the memory cell array dependent on a row address of the internally generated address;
• a column selecting circuit to select one or more columns of the memory cell array dependent on a column address of the internally generated address;
• a page buffer circuit to sense data from selected memory cells of the selected columns;
• a read initiate circuit to generate a second detection signal when the power supply voltage reaches the predetermined detection voltage and the control signal is active;
• and
• a read controller to control a sensing operation of the page buffer circuit responsive to the second detection signal;
• and
• wherein the read initiate circuit is to be selectively controlled by the control signal of the control circuit based upon the device information and whether or not the power supply voltage is lower than the predetermined detection voltage.

A flash memory device comprising:

• a plurality of nonvolatile memory cells arranged in rows and columns;
• a detector to generate a first detection signal when a power supply voltage is lower than a predetermined threshold;
• addressor to internally generate an address responsive to the first detection signal of the detector;
• a read circuit to read data of the plurality of memory cells responsive to an internally generated address of the addressor;
• and
• a controller to determine device information and to check a level of the power supply voltage;
• the controller operable to control the read circuit based upon its device information determination and the supply level check;
• and
• the power detecting circuit to be activated selectively under the control of the control circuit based upon the device information determination and the level check.

A method of operating a flash memory device within a system, comprising:

• determining, during a duration of the system power-up, whether the memory device is to be set as a boot-up memory of the system;
• reading boot-up data stored in the memory device during the system power-up when the memory device is determined to be set as boot-up memory;
• and
• entering, after the system power-up, a ready mode to allow normal write/read operation of the memory device when the memory device is determined not to be set as a boot-up memory.