Nonvolatile ferroelectric memory control device

A nonvolatile ferroelectric memory control device comprising:

• a column address latch for latching column addresses according to a chip enable signals;
• a column decoder for decoding the latched column address;
• a chip enable signal transition detector for detecting whether the chip enable signal is transited and then outputting a chip enable transition detecting signals;
• a block selection address latch for latching block selection addresses according to the chip enable signals;
• an address transition detector for detecting whether the latched block selection address is transited and then outputting a address transition detecting signals;
• a synthesizer for outputting the transition synthesizing signal according to input of the chip enable transition detecting signal when a power-on reset signal is inputted and then outputting the transition synthesizing signal according to the address transition detecting signal;
• and
• a chip control signal generator for outputting control signals controlling chip operation according to the transition synthesizing signal.

A nonvolatile ferroelectric memory control device comprising:

• a pre-latch unit for latching row addresses inputted according to a latch enable signals;
• an address latch unit for latching outputs of the pre-latch unit according to chip enable signals and outputting a address transition detecting signals;
• a FRAM memory array wherein its driving is controlled according to the address transition detecting signal applied from the address latch unit;
• a data register array for storing the row address and the row address data applied from the FRAM memory array;
• a comparator for comparing row addresses stored in the data register array and the inputted row addresses and then outputting the latch enable signals or a register enable signals according to the comparison result;
• and
• an input/output controller for controlling data input/output of the FRAM memory array and outputting the row address data stored in the data register array according to the register enable signals into data buses.