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US 6,661,695 B2Granted
Capacitance sensing technique for ferroelectric random access memory arrays
AssigneeRamtron International Corporation
InventorDavid Fisch
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AssigneeRamtron International Corporation
InventorDavid Fisch
Estimating the term…
A capacitance sensing technique for ferroelectric random access, memory devices and arrays which enables fast sensing operations to be performed allowing for low latency “read” operations and thereby providing overall system performance advantages. Through the use of the technique of the disclosed, concurrent polling and reading of data may be achieved prior to pulsing (or driving) the plate line. This then allows the memory “restore” function to be hidden behind the “read” data stream at the memory device output pins. In accordance with the technique of the present invention, the sensing may begin prior to pulsing the plate line and it is the sensing process itself which interrogates the memory and concurrently prepares the data for the outputs. In this manner, it is the pulsing of the plate line after the data is sensed that performs the “restore” and this operation is not a portion of the “read” access time critical path.
A sensing technique for an integrated circuit device comprising a memory array including a plurality of ferroelectric memory cells coupled to complementary bit lines, the technique comprising:
A method for sensing the data state stored in a ferroelectric memory cell selectively couplable to a sense amplifier, said method comprising:
An integrated circuit device including a memory array, said device comprising:
An integrated circuit device including a memory array comprising at least one pair of complementary bit lines coupled to at least one sense amplifier, said device comprising:
Dependencies are inferred from the claim text.