Cam circuit with separate memory and logic operating voltages

A content addressable memory (CAM) circuit comprising:

• a plurality of data lines;
• a plurality of CAM cells, each CAM cell including:
• a memory cell having a storage node for storing a first data value, said memory cell being connected to a first operating voltage, and
• a logic portion including a comparator for receiving the first data value from the memory cell and a second data value transmitted on an associated data line of the plurality of data lines during a compare operation;
• and
• data line control circuit for controlling voltage signals transmitted on the plurality of data lines,
• wherein the data line control circuit is connected to a second operating voltage, and
• wherein the first operating voltage is greater than the second operating voltage.

A content addressable memory (CAM) circuit comprising:

• a plurality of CAM cells, each CAM cell including:
• a memory cell having a storage node for storing a first data value, said memory cell being connected to a first operating voltage, and
• logic portion including a comparator for receiving the first data value from the memory cell and a second data value transmitted on an associated data line during a compare operation;
• a match line coupled to the plurality of memory cells;
• and
• sensing means for measuring the voltage signal transmitted on said match line, said sensing means being connected to a second operating voltage, and
• wherein the first operating voltage is greater than the second operating voltage.

A content addressable memory (CAM) circuit comprising:

• a plurality of DRAM CAM cells, each CAM cell including:
• a memory cell having a storage node for storing a first data value, and
• a logic portion including a comparator for receiving the first data value from the memory cell and a second data value transmitted on an associated data line during a compare operation;
• a plurality of bit lines, each bit line being connected to an associated memory cell of the plurality of CAM cells;
• a bit line control circuit for controlling voltage signals transmitted on the plurality of bit lines;
• a match line coupled to the plurality of memory cells;
• and
• a match line control circuit for controlling a voltage signal transmitted on the match line,
• wherein the bit line control circuit is connected to a first operating voltage,
• wherein the match line control circuit is connected to a second operating voltage, and
• wherein the first operating voltage is greater than the second operating voltage.