Content addressable memory having dynamic match resolution

A method, comprising:

• comparing, in a first compare operation, first comparand data with first data stored in a row of content addressable memory (CAM) cells to generate a first comparison result;
• comparing, in a second compare operation, second comparand data with second data to generate a second comparison result;
• generating a timing signal in response to the second comparison result;
• and capturing the first comparison result in response to the timing signal, wherein the second compare operation further comprises:
• comparing third comparand data with the second data to generate a third comparison result;
• and
• selecting either the second or third comparison result to generate the timing signal.

A method, comprising:

• performing a first compare operation in a row of content addressable memory (CAM) cells;
• and
• performing a second compare operation to determine when the first compare operation is complete, wherein the second compare operation comprises:
• comparing first data with second data to generate a first comparison result;
• comparing the first data with third data to generate a second comparison result;
• and
• selecting either the first or second comparison result to determine when the first compare operation is complete.

A content addressable memory (CAM) architecture, comprising:

• means for performing a first compare operation in a row of CAM cells;
• and means for performing a second compare operation to determine when the first compare operation is complete, wherein the means for comparing the second compare operation comprises:
• means for comparing first data with second data to generate a first comparison result;
• means for comparing the first data with third data to generate a second comparison result;
• and
• means for selecting either the first or second comparison result to determine when the first compare operation is complete.

A dynamic timing generator circuit for a content addressable memory (CAM) architecture including a CAM array having a plurality of CAM cells, the dynamic timing generator circuit comprising:

• a match comparison timing circuit including a first compare circuit to compare first data with second data and assert a first signal indicative of when the first and second data match;
• a mis-match comparison timing circuit including a second compare circuit to compare third data with fourth data and assert a second signal indicative of when the third and fourth data mis-match;
• and
• a select circuit coupled to receive and select one of the first and second signals for capturing comparison results between a comparand and data stored in the CAM array.

A method, comprising:

• asserting a first signal when first data matches second data;
• asserting a second signal when the first data does not match third data;
• and
• capturing match results from a plurality of content addressable memory (CAM) cells in response to one of the first or second signals.

A comparison timing circuit comprising:

• a first timing circuit comprising:
• a first compare circuit for successively comparing first data with second data and third data, wherein the second data matches the first data and the third data mis-matches the first data;
• and
• a first sense circuit coupled to an output of the first compare circuit to sense first compare results between the first data and the second and third data to generate a first signal;
• a second timing circuit comprising:
• a second compare circuit for successively comparing fourth data with fifth data and sixth data, wherein the fifth data matches the fourth data and the sixth data mis-matches the fourth data;
• and
• a second sense circuit coupled to an output of the second compare circuit to sense second compare results between the fourth data and the fifth and sixth data to generate a second signal;
• and
• an interleaver circuit coupled to receive the first and second signals.