Splitting grouped writes to different memory blocks
AssigneeSun Microsystems, Inc.
InventorsMichael G. Lavelle, Ewa M. Kubalska, Elena M. Ing
Life of this patent
Estimating the term…
Abstract
A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.
Claims37
A graphics system comprising:
- a memory configured to receive and store a tile of graphics data;
- a boundary violation detector connected to the memory, wherein the boundary violation detector is configured to receive an address corresponding to the tile and determine if the tile will cross a memory block boundary;
- and
- a write controller connected to the memory and the boundary violation detector, wherein the write controller is configured to split the tiles that cross the memory block boundaries.
A method for rendering graphics data, the method comprising:
- receiving a tile of graphics data;
- receiving a target memory address for the tile of graphics data;
- decimating the target memory address into X and Y components, wherein the X and Y components are virtual memory addresses, wherein the minimum value of the X and Y components is zero, wherein the maximum value of the X component is less than an integer constant j times the width of a block in the memory, wherein the maximum value of the Y component is less than an integer constant k times the height of a block in the memory;
- incrementing the X component by a number equal to the tile width minus 1;
- incrementing the Y component by a number equal to the tile height minus 1;
- dividing the incremented X component by the width of the block of memory;
- dividing the incremented Y component by the height of the block of memory;
- examining the remainders of each of the divisions, wherein if one or more of the remainders are zero, then a crossing of the associated block of memory boundary is indicated;
- storing the tile of graphics data in a number of blocks of memory according to the crossing of the boundary or boundaries of the block of memory;
- retrieving the tile of graphics data from the block or blocks of memory;
- and
- displaying the retrieved tile of graphics data on a display device.
A method for storing a tile of graphics data, wherein the tile crosses one or more memory block boundaries, wherein the width of the memory block is equal to 2n samples, and wherein the height of the memory block is equal to 2m samples, the method comprising:
- receiving a target memory address of a tile, wherein the target memory address is within a linear address space of the memory, and wherein the target memory address corresponds to a storage location, wherein the storage location corresponds to the first element of the tile;
- decimating the target memory address into four binary fields, f1, f2, f3 and f4, wherein each field comprises a unique subset of contiguous bits from the target memory address;
- examining f1, wherein if the content of f1 is greater than n minus the tile width, then a horizontal boundary violation is indicated;
- examining f3, wherein if the content of f3 is greater than to m minus the tile height, then a vertical boundary violation is indicated;
- splitting the tile into sub-tiles in accordance with the horizontal and vertical boundary violation indications;
- and
- storing the sub-tiles in the memory.
A method for storing an array of pixels or samples, wherein the array crosses one or more memory block boundaries, wherein the memory block width is equal to 2n samples, wherein the memory block height is equal to 2m samples, wherein the width of the array of pixels or samples is equal to two, and wherein the height of the array of pixels or samples is equal to two, the method comprising:
- receiving a target memory address of the array, wherein the target memory address is within a linear address space of a memory, and wherein the target memory address corresponds to the storage location of the element residing in the first row of the first column of the array;
- and
- decimating the target memory address into four binary fields, f1, f2, f3 and f4, wherein each field comprises a unique subset of contiguous bits from the target memory address,
- examining f1, wherein if all the bits within f1 are equal to 1, then a horizontal boundary violation is indicated;
- examining f3, wherein if all the bits of f3 are equal to 1, then a vertical boundary violation is indicated;
- splitting the tile into sub-tiles in accordance with the horizontal and vertical boundary violation indications;
- and
- storing the sub-tiles in the memory.
A method for storing an array of graphics data, the method comprising:
- receiving a two-dimensional array of graphics data, wherein the array comprises a number of samples, wherein the number of samples is greater than one;
- determining whether the array crosses one or more memory block boundaries;
- splitting the arrays that cross boundaries into sub-arrays, wherein each sub-array comprises a subset of the samples contained in the corresponding array, wherein each sub-array lies completely within a single memory block;
- examining the sub-arrays for enabled samples, wherein enabled samples of the sub-arrays are flagged;
- and
- generating a sequence of write operations to store the sub-arrays, wherein the number of write operations is equal to the number of sub-arrays with enabled samples.
A graphics system comprising:
- a memory configured to receive and store a tile of graphics data;
- a boundary violation detector connected to the memory, wherein the boundary violation detector is configured to receive an address corresponding to the tile and determine if the tile will cross a memory block boundary;
- a write controller connected to the memory and the boundary violation detector, wherein the write controller is configured to split the tiles that cross the memory block boundaries;
- and
- a bus interface, wherein the bus interface is configured to couple the graphics system to a host system, wherein the bus interface is configured to receive the graphics data from the host system.
Dependencies are inferred from the claim text.