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US 6,661,298 B2Granted
Method and apparatus for a digital clock multiplication circuit
AssigneeNational University of Singapore
InventorsKin Mun Lye, Jurianto Joe
Life of this patent
Estimating the term…
Abstract
A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.
Claims11
A frequency multiplication method comprising:
- receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;
- applying the input signal to a first circuit, the first circuit configured to produce a first plurality of pulses in response to a signal level of the first half cycle;
- applying the input signal to a second circuit, the second circuit configured to produce a second plurality of pulses in response to a signal level of the second half cycle;
- and
- combining the first plurality of pulses with the second plurality of pulses to produce an output signal that is representative of a frequency-multiplied version of the input signal, and wherein pulse widths of the first and second plurality of pulses depends on the signal level.
2 more elements
A frequency multiplication circuit comprising:
- a circuit input for receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;
- a first circuit portion having a first input coupled to receive at least the first half cycle of the input signal, the first circuit portion responsive to a signal level of the first half cycle by producing a first plurality of pulses;
- a second circuit portion having a second input coupled to receive at least the second half cycle of the input signal, the second circuit portion responsive to a signal level of the second half cycle by producing a second plurality of pulses;
- and
- a third circuit operable to combine the first and second plurality of pulses to produce an output signal and wherein pulse widths of the first and second plurality of pulses depend on the signal level.
2 more elements
A frequency multiplication circuit comprising:
- an input for receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;
- first circuit means coupled to the input for producing first pulses in response to a signal level of first half cycles of the input signal;
- second circuit means coupled to the input for producing second pulses in response to a signal level of second half cycles of the input signal;
- and
- a combining means coupled to receive the first and second pulses for producing an output signal comprising the first and second pulses,
- the first circuit means characterized by a transfer function having a stable operating region and an unstable operating region,
- the second circuit means characterized by a transfer function having a stable operating region and an unstable operating region;
- and wherein pulse widths of the first and second pulses depends on the signal level.
5 more elements
Dependencies are inferred from the claim text.