Controllable crystal oscillator

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, the crystal oscillator circuit including a voltage variable capacitive element responsive to the control input, an AT-cut quartz resonator operably linked to the varactor, and a gain stage for energizing the quartz resonator;
• the quartz resonator being adapted to resonate in fundamental mode at about 19.44 Megahertz;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit having a-preselected divider ratio of about 32:1 operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal,
• the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal;
• and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital output signal having substantially the same frequency as the controlled-frequency signal,
• the oscillator exhibiting an operating frequency within the area defined between the following two equations:
• f1output=0.04526(Vcontrol)+621.9430 Megahertz
• f2output=0.04526(Vcontrol)+621.9679 Megahertz
• for Vcontrol values in the range of about 0.15 volts to about 3.15 volts, where Vcontrol is a DC voltage level of the voltage-variable input.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, the crystal oscillator circuit including a discrete varactor responsive to the control input, an AT-cut quartz resonator operably linked to the varactor, and a gain stage for energizing the quartz resonator;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit having a preselected divider ratio operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal,
• the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal;
• and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital logic output signal having substantially the same frequency as the controlled-frequency signal,
• wherein the oscillator exhibits an operating digital output frequency within the area defined between the following two equations:
• f1output=0.04526(Vcontrol)+621.9430 Megahertz
• f2output=0.04526(Vcontrol)+621.9679 Megahertz
• for Vcontrol values in the range of about 0.15 volts to about 3.15 volts, where Vcontrol is a DC voltage level of the voltage-variable input.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a variable capacitance unit having and being responsive to a control input for providing a variable capacitive load;
• a resonator gain stage;
• a quartz resonator operably linked to the gain stage and the variable capacitance unit for generating a driving signal whereby the control input may adjust the capacitive load and a frequency of the driving signal;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal,
• the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal, and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital logic output signal having substantially the same frequency as the analog controlled-frequency signal.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a variable capacitance unit having and being responsive to a control input for providing a variable capacitive load;
• a resonator gain stage;
• a quartz resonator operably linked to the gain stage and the variable capacitance unit for generating a driving signal whereby the control input may adjust the capacitive load and a frequency of the driving signal;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• and
• a frequency divider circuit operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal,
• the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal,
• wherein the oscillator exhibits an operating digital output frequency within the area defined between the following two equations:
• f1output=0.04526(Vcontrol)+621.9430 Megahertz
• f2output=0.04526(Vcontrol)+621.9679 Megahertz
• for Vcontrol values in the range of about 0.3 volts to about 3 volts, where Vcontrol is a DC voltage level of the voltage-variable input.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a temperature sensor;
• a temperature compensation logic operably linked to the temperature sensor for generating a capacitance adjustment;
• a variable capacitance circuit having and being responsive to a control input for providing a variable capacitive load, the variable capacitance circuit also being responsive to the capacitance adjustment;
• a resonator gain stage;
• a quartz resonator operably linked to the gain stage and the variable capacitance circuit for generating a driving signal;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit having a preselected divider ratio operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal, the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal;
• and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital logic output signal having substantially the same frequency as the controlled-frequency signal.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, the crystal oscillator circuit including a discrete varactor responsive to the control input, an AT-cut quartz resonator operably linked to the varactor, and a gain stage for energizing the quartz resonator;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit having a preselected divider ratio operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced-frequency feedback signal in response to the controlled-frequency signal,
• the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal;
• and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital logic output signal having substantially the same frequency as the controlled-frequency signal,
• wherein the oscillator exhibits an operating digital output frequency within the area defined between the following two equations:
• f1output=0.04526(Vcontrol)+621.9430 Megahertz
• f2output=0.04526(Vcontrol)+621.9679 Megahertz
• at oscillator operating temperatures in the range of about −30 degrees Celsius to about 85 degrees Celsius (° C.) and for Vcontrol values in the range of about 0.15 volts to about 3.15 volts, where Vcontrol is a DC voltage level of the voltage-variable input.

A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising:

• a temperature compensated oscillator module including a quartz resonator and providing a driving signal having an oscillation frequency substantially independent of operating temperature;
• a discrete varactor operably linked to the quartz resonator of the temperature compensated oscillator module for providing a variable capacitive load;
• a voltage-variable control input operably linked to the discrete varactor;
• a resonator gain stage;
• a quartz resonator operably linked to the gain stage and the voltage-variable capacitance means for generating a driving signal whereby the voltage-variable control input may adjust the capacitive load and a frequency of the driving signal;
• a phase detector circuit for generating a phase offset signal;
• a filter which operates on the phase offset signal to produce a VCO control signal;
• a voltage controlled-oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal;
• a frequency divider circuit having a preselected divider ratio operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal, the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal;
• and
• a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital logic output signal having substantially the same frequency as the controlled-frequency signal.