Phase-locked loop circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHisae Terashima, Hiroyuki Ueda
Life of this patent
Estimating the term…
Abstract
A phase error signal indicating a most recent phase difference between an input clock signal and a feed-back signal is produced in a phase comparing unit. Also, the phase difference of the phase error signal is monitored in an abnormal condition detecting unit. When the phase difference is higher than a threshold value, the abnormal condition detecting unit judges that the input clock signal is set in an abnormal condition, and a frequency-controlled clock signal is produced in the voltage controlled oscillator according to the phase error signal. Therefore, the oscillation clock signal can be output without changing a phase of the oscillation clock signal while suppressing wonders or jitters.
Claims11
A phase-locked loop circuit comprising:
- a phase comparator for comparing a phase of an input clock signal having a prescribed frequency and a phase of a feed-back signal and outputting a phase error signal indicating a phase difference between the input clock signal and the feed-back signal;
- a low pass filter for smoothing the phase error signal to produce a voltage controlled signal;
- a voltage controlled oscillator for producing an oscillation clock signal according to the voltage controlled signal produced by the low pass filter and outputting the oscillation clock signal;
- and
- a frequency divider for dividing a frequency of the oscillation clock signal produced by the voltage controlled oscillator to produce the feed-back signal output to the phase comparator,
- characterized in that the phase-locked loop circuit further comprises:
- an abnormal condition detector for monitoring a pulse width of the phase error signal output from the phase comparator and judging the input clock signal to be in an abnormal condition in a case where the pulse width of the phase error signal exceeds a prescribed threshold value;
- a phase difference storage for storing the phase error signal output from the phase comparator;
- a selector for selecting either the phase error signal output from the phase comparator or the phase error signal stored in the phase difference storage and outputting the selected phase error signal to the low pass filter;
- and
- a control unit for controlling the selector to select the phase error signal stored in the phase difference storage in a case where it is judged by the abnormal condition detector that the input clock signal is in an abnormal condition.
Dependencies are inferred from the claim text.