Level converter circuit
AssigneeFujitsu Limited
InventorsNaoaki Naka, Junko Nakamoto
Life of this patent
Estimating the term…
Abstract
In the level converter circuit, when input signal is L level, a first NMOS transistor and a first PMOS transistor P1 are turned on by a first power supply potential, a second power supply potential is output to a first output terminal, a second NMOS transistor is turned on, and thereby, a reference potential VSS is output to a second output terminal. On the other hand, when the input signal is H level, a third NMOS transistor is turned on, the reference potential is output to the first output terminal, a fourth NMOS transistor and a second PMOS transistor are turned on, and thereby, the first power supply potential VDH is output to the second output terminal.
Claims10
A level converter circuit comprising:
- an input terminal;
- a first output terminal and a second output terminal each of which outputs a differential signal;
- a logical element which outputs a reference potential or a first power supply potential based on the potential of the input signal received from said input terminal;
- a first N-channel field effect transistor which outputs the reference potential when said logical element has output the first power supply potential;
- a first P-channel field effect transistor which received the reference potential output by said first N-channel field effect transistor, and outputs a second power supply potential to said first output terminal;
- a second N-channel field effect transistor which outputs the reference potential to said second output terminal when said logical element has output the first power supply potential;
- a third N-channel field effect transistor which outputs the reference potential to said first output terminal when said logical element has output the reference potential;
- a fourth N-channel field effect transistor which outputs the reference potential when said logical element has output the reference potential;
- and
- a second P-channel field effect transistor which receives the reference potential output by said fourth N-channel field effect transistor, and outputs the second power supply potential to said second output terminal.
Dependencies are inferred from the claim text.