Digitally controllable internal clock generating circuit of semiconductor memory device and method for same
OwnerNam-Seog Kim, Yong-Jin Yooninventors
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Abstract
An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.
Claims17
An internal clock generating circuit of a semiconductor device comprising:
- a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock;
- a thermometer converter for outputting a thermometer code value in response to an input selection data;
- and
- a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value, wherein the multiplexer selectively outputs one of the plurality of clocks applied from the delay chain by dividedly multiplexing the thermometer code value into two stages of upper and lower bits.
A method of generating clock signals in a semiconductor device comprising the steps of:
- generating multi-phase clock signals by adjusting an input clock signal through a delay chain having a plurality of delay units;
- decoding a thermometer code value in accordance with selection data;
- outputting one of the plurality of clock signals in response to the thermometer code value, wherein the step of outputting one of the plurality of clock signals comprises the step of selectively outputting by dividedly multiplexing the thermometer code value into two stages of upper and lower bits;
- and
- restoring a pulse shape of the output clock signal into its original state and outputting it as a delay-controlled internal clock signal.
A semiconductor clock signal circuit, comprising:
- means for generating multi-phase clock signals by adjusting an input clock signal through a delay chain having a plurality of delay units;
- means for decoding a thermometer code value in accordance with selection data;
- means for outputting one of the plurality of clock signals in response to the thermometer code value, wherein the means for outputting one of the plurality of clock signals comprises means for selectively outputting by dividedly multiplexing the thermometer code value into two stages of upper and lower bits;
- and
- means for restoring a pulse shape of the output clock signal into its original state and outputting it as a delay-controlled internal clock signal.
Dependencies are inferred from the claim text.