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US 6,661,271 B1Granted
Multi-phase edge rate control for SCSI LVD
AssigneeLSI Logic Corporation
InventorsBrian E. Burdick, Matthew S. Von Thun
Life of this patent
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Abstract
An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
Claims16
An apparatus comprising:
- a plurality of serially cascaded delay cells each (i) comprising a latch and (ii) configured to generate a phase of a multi-phase signal and an intermediate signal, wherein (i) each of said delay cells is configured to respond to a bias signal and one of said intermediate signals, (ii) a first of said delay cells is configured to respond to an input signal, (iii) said apparatus further comprises a delay devise and a logic gate configured to receive said input signal and (iv) an output of said logic gate is presented to said first delay cell.
A method of generating a multi-phase signal comprising the steps of:
- (A) serially cascading a plurality of delay cells each (i) comprising a latch and (ii) configured to respond to a bias signal and one of a plurality of intermediate signals, wherein a first of said delay cells is configured to respond to an input signal;
- (B) generating one of said intermediate signals and a phase of said multi-phase signal at each respective one of said delay cells;
- (C) presenting the intermediate signal of the preceding delay cell to a data input of a latch of the succeeding delay cell;
- and
- (D) presenting the intermediate signal of the delay cell to a reset input of said latch.
2 more elements
An apparatus comprising:
- a plurality of serially cascaded delay cells each (i) comprising a latch and (ii) configured to generate a phase of a multi-phase signal and an intermediate signal, wherein (i) each of said delay cells is configured to respond to a bias signal and one of said intermediate signals, (ii) a first of said delay cells is configured to respond to an input signal, (iii) each succeeding one of said delay cells is further configured to respond to the intermediate signal presented by a preceeding one of said delay cells and (iv) each latch comprises (a) a data input configured to receive the intermediate signal of the preceeding delay cell and (b) a reset input configured to receive the intermediate signal of the delay cell via a feedback path.
Dependencies are inferred from the claim text.