Coarse calibration circuit using variable step sizes to reduce jitter and a dynamic course calibration (DCC) circuit for a 2 GHz VCO

A calibration system for a Phase Locked Loop (PLL) comprising:

• a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency,
• a charge pump connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter,
• the low pass filter providing a filtered error signal to the VCO and to a comparator system,
• the comparator system providing a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit, and
• a calibration means for continuously providing incremental calibration input to the VCO after a time delay,
• whereby the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.

A calibration system for a Phase Locked Loop (PLL) comprising:

• a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency, the VCO comprising a voltage to current (V-I) converter connected to provide an input to a current controlled oscillator (ICO),
• a charge pump connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter,
• the low pass filter providing a filtered error signal to the VCO and to a comparator system,
• the comparator system providing a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit,
• a calibration means for continuously providing incremental calibration input to the VCO after a time delay, the calibration means including a Dynamic Course Correction (DCC) circuit and a Digital to Analog Converter (DAC) and the DAC provides an input to the ICO,
• the calibration means beginning a calibration cycle by sampling the output of the comparator system at sampling times and then determining when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time, and
• the calibration means determining whether the calibration has corrected a detected error and repeating the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle,
• whereby the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.