Programmable divider with built-in programmable delay chain for high-speed/low power application
AssigneeBroadcom Corporation
InventorsDerek Tam, Takayuki Hayashi
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Abstract
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.
Claims10
An apparatus comprising:
- means for receiving input clock signals to produce output signals responsive thereto;
- and
- means for forming a feedback loop with the means for receiving input clock signals, the means for forming a feedback loop being configurable to (i) selectively receive selected ones of the output signals and (ii) control divide characteristics associated with the means for receiving input clock signals based upon the selected output signals.
An apparatus comprising:
- means for processing an input clock signal and producing first output signals in response thereto;
- means for (i) receiving the first output signals, (ii) performing logic operations thereon, and (iii) producing second output signals;
- and
- means for receiving the second output signals and having an output coupled to an input of the means for processing;
- wherein characteristics of the means for processing are selectable based upon a particular number of configured means for receiving first output signals.
A method comprising:
- (a) receiving input clock signals in a synchronous counter and producing output signals responsive thereto;
- (b) forming a feedback loop with the synchronous counter using a control circuit;
- and
- (c) configuring the control circuit to (i) receive selected ones of the output signals and (ii) control characteristics of the synchronous counter based upon the selected output signals.
Dependencies are inferred from the claim text.