Programmable interconnect circuit with a phase-locked loop
AssigneeLattice Semiconductor Corporation
InventorsOm P. Agrawal, Jinghui Zhu, Kuang Chi, ChienKuang Chen
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Abstract
A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O cells may all be clocked in phase. In addition, the phase-locked loop may provide an external clock signal to the programmable interconnect circuit's routing structure such that external devices may clocked in phase with the external clock signal.
Claims16
A programmable interconnect circuit, comprising:
- a plurality of input/output (I/O) cells, each I/O cell having a register associated with a pin:
- a routing structure configured to receive a signal from each I/O cell's register and programmably route the received signal to any of the remaining I/O cells' registers;
- a phase-locked loop (PLL) operable to receive an external clock signal and provide an internal clock signal to the resisters in the I/O cells, wherein the PLL is operable to provide a PLL external clock signal derived from the eternal clock signal and to couple the PLL external clock signal to one of the I/O cells, and wherein the routing structure is configurable to distribute the PLL external clock signal to any of the I/O cells' registers such that external devices coupled to the pins associated with the I/O cells receiving the PLL external clock signal are configurable to be synchronously clocked with respect to the external clock signal.
A programmable interconnect circuit, comprising:
- a plurality of input/output (I/O) cells arranged into a plurality of N I/O blocks, wherein N is an integer and each I/O block includes at least two I/O cells and each I/O cell includes a multiplexer and a register associated with a pin of the programmable interconnect circuit;
- a plurality of N routing structures corresponding to the plurality of N I/O blocks, each routing structure configured to receive signals from the plurality of I/O cells and programmably route the signals to each I/O cell within the routing structure's I/O block;
- and
- a phase-locked loop (PLL) operable to receive an external clock signal and provide an internal clock signal to the registers in the I/O cell such that the register in the I/O cells are configurable to be synchronously clocked with respect to the external clock signal.
A programmable interconnect circuit, comprising:
- a plurality of input/output (I/O) cells operable to receive input signals and to transmit output signals;
- a routing structure coupled to the I/O cells and operable to receive input signals from I/O cells and to provide output signals to I/O cells;
- and
- a phase-locked loop coupled to an I/O cell and operable to provide a PLL clock signal as an input signal to the I/O cell, the PLL clock signal being routed from the I/O cell to the routing structure, the routing structure operable to provide the PLL clock signal as an output signal to multiple I/O cells.
Dependencies are inferred from the claim text.