High voltage detector
AssigneeHynix Semiconductor Inc.
InventorYong-Ki Kim
Life of this patent
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Abstract
A high voltage detector used in an integrated circuit having a high voltage generator for generating high voltage boosting internal voltage is disclosed. The high voltage detector may include a reference voltage supply for supplying reference voltage and a low voltage detector for comparing the reference voltage and the internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage level is less than a predetermined voltage level. The high voltage detector may also include a control signal outputting unit, which is configured as a current mirror and the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level.
Claims29
A high voltage detector used in an integrated circuit having a high voltage generator for generating a boosted internal voltage, comprising:
- a reference voltage supplying unit for supplying a reference voltage;
- a low voltage detecting unit for comparing the reference voltage and an internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage is less than a predetermined voltage level;
- and
- a control signal outputting unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level;
- the control signal outputting unit comprises:
- a first node:
- a second node;
- a pass gate unit having a resistance and connected between the first and second nodes, wherein the resistance is varied between the first and second nodes in response to the low voltage detecting signal;
- and
- an output voltage generating unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for outputting the pumping control signal of the first or second potential level according to the resistance of the pass gate.
A high voltage detector used in an integrated circuit having a high voltage generator for generating a boosted internal voltage, comprising:
- a reference voltage supplying unit for supplying a reference voltage;
- a low voltage detecting unit for comparing the reference voltage and an internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage is less than a predetermined voltage level;
- and
- a control signal outputting unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level;
- the pass gate unit comprises:
- a first PMOS transistor, which is connected to the first and second nodes and to a gate of which the low voltage detecting signal is applied;
- and
- a second PMOS transistor, which is connected to the first PMOS transistor and a gate of which is connected to a ground voltage level.
A high voltage detector used in an integrated circuit having a high voltage generator for generating a boosted internal voltage, comprising:
- a reference voltage supplying unit for supplying a reference voltage;
- a low voltage detecting unit for comparing the reference voltage and an internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage is less than a predetermined voltage level;
- and
- a control signal outputting unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level;
- the output voltage generating unit comprises:
- a third PMOS transistor, which is connected to the high voltage and the first node and a gate of which is connected to a ground voltage level;
- a first NMOS transistor, which is connected to the second node and the ground voltage level and a gate of which is connected to second node;
- a fourth PMOS transistor, which is connected to the internal voltage and a gate of which is connected to the ground voltage level;
- a second NMOS transistor, which is connected to the fourth PMOS transistor and the ground voltage level and a gate of which is connected to the second node together with the first NMOS transistor;
- a first inverter for inverting voltage between the fourth PMOS transistor and the second NMOS transistor;
- and
- a second inverter for inverting an output of the first inverter.
A high voltage detector used in an integrated circuit having a high voltage generator for generating a boosted internal voltage, comprising:
- a reference voltage supplying unit for supplying a reference voltage;
- a low voltage detecting unit for comparing the reference voltage and an internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage is less than a predetermined voltage level;
- and
- a control signal outputting unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level;
- the low voltage detecting unit comprises:
- sixth and seventh PMOS transistors, which are connected to high voltage and the gates of which are connected each other;
- a third NMOS transistor, which is connected to the sixth PMOS transistor and to the gate of which the reference voltage is applied;
- a fourth NMOS transistor, which is connected to the seventh PMOS transistor and a ground voltage level and to the gate of which the internal voltage is applied;
- a third inverter, which is enabled in response to the high voltage, for inverting a voltage level between the seventh PMOS transistor and the fourth NMOS transistor;
- and
- a fourth inverter, which is enabled in response to the high voltage, for inverting an output of the third inverter and outputting the low voltage detecting signal of a first or a second potential level.
Dependencies are inferred from the claim text.