Differential voltage limiter
AssigneeADC DSL Systems, Inc.
InventorGeorge Bertram Dodson, III
Life of this patent
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Abstract
A low cost differential voltage limiter circuit provides a feedback to regulate a voltage output of a voltage source. In one embodiment, the limiter circuit includes a transistor coupled to outputs of first and second voltage sources. If a differential voltage between the two sources exceeds a predetermined threshold, the output voltage of the higher source is reduced. In one embodiment, a PNP transistor is used to regulate the high voltage source.
Claims17
A voltage source circuit comprising:
- a first voltage source having an output to provide a first output voltage;
- a second voltage source having an output to provide a second output voltage, wherein the second output voltage is less than the first output voltage;
- and
- a differential limiter circuit coupled to the first and second voltage sources, the differential limiter circuit comprises a feedback transistor coupled to a control input of the first voltage source.
A voltage source circuit comprising:
- a first voltage source having an output to provide a first output voltage;
- a second voltage source having an output to provide a second output voltage, wherein the second output voltage is less than the first output voltage;
- a PNP feedback transistor having base, emitter and collector nodes, the collector node is coupled to a control input of the first voltage source;
- a resistor divider circuit coupled between the outputs of the first and second voltage sources, a center node of the resistor divider is coupled to the base node of the PNP transistor;
- and
- a degeneration resistor coupled between the first voltage source and the emitter.
A voltage source circuit comprising:
- a first voltage source having an output to provide a first output voltage of about 3.3 volts;
- a second voltage source having an output to provide a second output voltage of about 2.5 volts;
- a first resistor divider having a first resistor coupled between the output of the first voltage source and the control node, and a second resistor coupled between the control node and ground, wherein a voltage on the control node controls the first output voltage;
- a PNP feedback transistor having base, emitter and collector nodes, the collector node is coupled to a control input of the first voltage source;
- a second resistor divider circuit coupled between the outputs of the first and second voltage sources, a center node of the resistor divider is coupled to the base node of the PNP transistor;
- and
- a degeneration resistor coupled between the first voltage source and the emitter.
A method of controlling power supplies for an integrated circuit comprising:
- monitoring first and second power supply levels provided by first and second sources;
- and
- reducing the first power supply level if the first power supply level exceeds the second power supply level by a predetermined voltage, wherein the first power supply level is reduced by activating a feedback transistor coupled to a control node of a first power supply.
Dependencies are inferred from the claim text.