Low impedance power distribution structure for a semiconductor chip package

An electronic package comprising:

• a first substrate having a first surface, said first surface including a plurality of first features;
• a second substrate having a second surface, said second surface including a plurality of second features, wherein said second substrate is positioned substantially parallel to said first substrate, and wherein said second surface is located proximal to and facing said first surface;
• first electrical wires located on said first surface, said first electrical wires connecting selected ones of said plurality of first features on said first surface, wherein said first features and said first electrical wires are formed in substantially the same first plane;
• second electrical wires located on said second surface, said second electrical wires connecting selected ones of said second plurality of second features on said second surface, wherein said second features and said second electrical wires are formed in substantially the same second plane;
• wherein said first substrate and said second substrate are operationally bonded together;
• and
• wherein said first electrical wires, said second electrical wires, and said first features are under bump metallurgy (UBM).

A method of forming an electronic package comprising:

• providing a first substrate having a first surface, said first surface including a plurality of first features;
• providing a second substrate having a second surface, said second surface including a plurality of second features, wherein said second substrate is positioned substantially parallel to said first substrate, and wherein said second surface is located proximal to and facing said first surface;
• providing first electrical wires located on said first surface, said first electrical wires connecting selected ones of said plurality of first features on said first surface, wherein said first features and said first electrical wires are formed in substantially the same first plane;
• providing second electrical wires located on said second surface, said second electrical wires connecting selected ones of said plurality of second features on said second surface, wherein said second features and said second electrical wires are formed in substantially the same second plane;
• wherein said first substrate and said second substrate are operationally bonded together;
• and
• forming said first electrical wires, said second electrical wires, said first features, and said second features with under bump metallurgy (UBM) processing.