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US 6,661,064 B2Granted
Memory masking for periphery salicidation of active regions
AssigneeSTMicroelectronics S.r.l.
InventorsRobert Louis Hodges, Loi Ngoc Nguyen
Life of this patent
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Abstract
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
Claims5
A portion of an integrated circuit, comprising:
- a patterned gate layer overlying a surface of a substrate and defining gate regions of transistors forming memory cells;
- transistor diffusion regions relative to said gate regions of said memory cell transistors;
- supply routing diffusion regions for connecting said memory cell transistors to one or more of a source voltage source and a ground voltage;
- and
- a silicide layer over at least a portion of said supply routing diffusion regions but not over said transistor diffusion regions.
2 more elements
Dependencies are inferred from the claim text.