US 6,661,057 B1Granted

Tri-level segmented control transistor and fabrication method

OwnerRobert Dawson, Mark I. Gardner +5inventors

InventorsRobert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Jr., Mark W. Michael, Bradley T. Moore, Derick J. Wristers

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Abstract

A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

Claims15

Dependent claims

An integrated circuit comprising:

a substrate wafer;
a gate insulating layer formed on a surface of the substrate wafer;
a gate electrode formed on the gate insulating layer over the surface of the substrate wafer, the gate electrode having lateral sidewall surfaces;
a lightly-doped drain region doped into the substrate wafer self-aligned with the gate electrode;
an insulating dielectric layer formed on the lateral sidewall surfaces of the gate electrode;
spacers formed of a conductive material formed on the sidewall surfaces of the gate electrode, the spacers being electrically isolated from the gate electrode by the insulating dielectric layer and electrically isolated from the active region of the substrate wafer by the gate insulating layer;
an insulating layer formed on the substrate wafer overlying the gate electrode and the spacers, the insulating layer having a via extending through the insulating layer to a biasing spacer of the spacers;
a metal silicide layer formed on the gate electrode and formed on the spacers underlying the insulating layer, wherein the metal silicide layer formed on the gate electrode is separated by a minimum separation distance from the metal silicide layer formed on the spacers;
and
a conductor formed in the via extending through the insulating layer, the conductor for dynamically applying a biasing voltage to the biasing spacer for controlling voltage in the lightly-doped drain region.

7 more elements

An integrated circuit comprising:

a substrate wafer having an active region doped with impurities of a first conductivity type;
a gate insulating layer formed on a surface of the substrate wafer;
a gate electrode formed on the gate insulating layer over the surface of the substrate wafer, the gate electrode having lateral sidewall surfaces;
a lightly doped source region and a lightly doped drain region, the lightly doped regions being doped with impurities of a second conductivity type opposite in conductivity to the first conductivity type and formed in the active region of the substrate wafer, self-aligned with the gate electrode;
an insulating dielectric layer formed on the lateral sidewall surfaces of the gate electrode;
spacers formed of a conductive material formed on the sidewall surfaces of the gate electrode, the spacers being electrically isolated from the gate electrode by the insulating dielectric layer and electrically isolated from the active region of the substrate wafer by the gate insulating layer;
a doped source region and doped drain region having a doping concentration higher than the lightly-doped source region and the lightly-doped drain region, the doped source region and the doped drain region being self-aligned with the gate electrode and the spacers;
an insulating layer formed on the substrate wafer overlying the gate electrode and the spacers, the insulating layer having a via extending through the insulating layer to a biasing spacer of the spacers;
a metal silicide layer formed on the gate electrode and formed on the spacers underlying the insulating layer, wherein the metal silicide layer formed on the gate electrode is separated by a minimum separation distance from the metal silicide layer formed on the spacers;
and
a conductor formed in the via extending through the insulating layer, the conductor for dynamically applying a biasing voltage to the biasing spacer for controlling voltage in the lightly-doped drain region.

8 more elements

An integrated circuit chip including an integrated circuit comprising:

a substrate wafer having an active region doped with impurities of a first conductivity type;
a gate insulating layer formed on a surface of the substrate wafer;
a gate electrode formed on the gate insulating layer over the surface of the substrate wafer, the gate electrode having lateral sidewall surfaces;
a lightly doped source region and a lightly doped drain region, the lightly doped regions being doped with impurities of a second conductivity type opposite in conductivity to the first conductivity type and formed in the active region of the substrate wafer, self-aligned with the gate electrode;
an insulating dielectric layer formed on the lateral sidewall surfaces of the gate electrode;
spacers formed of a conductive material formed on the sidewall surfaces of the gate electrode, the spacers being electrically isolated from the gate electrode by the insulating dielectric layer and electrically isolated from the active region of the substrate wafer by the gate insulating layer;
a doped source region and doped drain region having a doping concentration higher than the lightly-doped source region and the lightly-doped drain region, the doped source region and the doped drain region being self-aligned with the gate electrode and the spacers;
an insulating layer formed on the substrate wafer overlying the gate electrode and the spacers, the insulating layer having a via extending through the insulating layer to a biasing spacer of the spacers;
a metal silicide layer formed on the gate electrode and formed on the spacers underlying the insulating layer, wherein the metal silicide layer formed on the gate electrode is separated by a minimum separation distance from the metal silicide layer formed on the spacers;
and
a conductor formed in the via extending through the insulating layer, the conductor for dynamically applying a biasing voltage to the biasing spacer for controlling voltage in the lightly-doped drain region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/056,836Filed 7 Apr 1998
Granted: 9 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/023
Of FETs having insulated gates [IGFET]: having multiple independently-addressable gate electrodes influencing the same channel
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs