Microelectronic capacitor structure embedded within microelectronic isolation region

A capacitor structure comprising:

• a semiconductor substrate having formed therein an isolation region adjoining an active region of the semiconductor substrate;
• a laterally asymmetric trench formed within the isolation region and bounded at one of its sides by a sidewall of the active region of the semiconductor substrate and at the remainder of its sides by a remaining portion of the isolation region;
• a capacitor node layer fanned into the laterally asymmetric trench, where the capacitor node layer contacts the sidewall of the active region of the semiconductor substrate and rises above the active region of the semiconductor substrate;
• a capacitor dielectric layer fanned upon the capacitor node layer;
• a capacitor plate layer formed upon the capacitor dielectric layer;
• an isolation dielectric layer formed upon the capacitor plate layer;
• and
• an interconnect layer formed over the isolation dielectric layer.