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US 6,661,040 B2Granted
Semiconductor device with insulating gate surrounded by impurity layers
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHiroyuki Takashino
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Abstract
A plurality of ONO films are provided in a matrix on a substrate surface. Gate electrodes are provided on each of the ONO films. Further provided in the substrate surface are n-type impurity layers and p-type impurity layers. Each of the p-type impurity layers is arranged between the n-type impurity layers. In a plan view of the substrate surface, the n-type impurity layers and the p-type impurity layers are arranged to surround the respective ONO films and the gate electrodes.
Claims6
A semiconductor memory device, comprising:
- a semiconductor substrate of a first conductivity type having a substrate surface;
- a first gate insulating film provided on said substrate surface, said first gate insulating film being capable of accumulating electric charges;
- a first gate electrode provided on said substrate surface through said first gate insulating film;
- and
- at least four impurity layers each being of a second conductivity type opposite to said first conductivity type, said at least four impurity layers being provided in said substrate surface to surround said first gate insulating film in a plan view of said substrate surface,
- wherein in said plan view of said substrate surface, said at least four impurity layers form a plurality of first pairs, each of said plurality of first pairs including impurity layers opposed to each other through said first gate insulating film, and
- each of said plurality of first pairs serves as a source/drain of a MISFET structure including said semiconductor substrate, said first gate insulating film and said first gate electrode.
4 more elements
Dependencies are inferred from the claim text.