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US 6,660,661 B1Granted
Integrated circuit with improved RC delay
AssigneeCypress Semiconductor Corporation
InventorsMira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh
Life of this patent
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Abstract
In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
Claims18
A method of fabricating an integrated circuit, comprising:
- forming a plurality of metal lines in a last metal level;
- and
- depositing a low-k dielectric to substantially fill a space extending between a sidewall of a metal line and a sidewall of another metal line in the plurality of metal lines.
A method of forming an integrated circuit, the method comprising:
- forming a plurality of metal lines on a dielectric layer in a last metal level;
- and
- applying a low-k dielectric between metal lines in the plurality of metal lines and directly on the dielectric layer.
Dependencies are inferred from the claim text.