US 6,660,618 B1Granted

Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems

AssigneeAdvanced Micro Devices, Inc.

InventorsSusan H. Chen, Paul R. Besser

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Abstract

Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer and thus serves as a partial etch stop layer, thereby preventing deleterious over-etching of the borderless via.

Claims14

Dependent claims

A method of manufacturing a semiconductor device comprising a multi-layer metallization system having reduced variation of vertical capacitance, which method comprises the sequential steps of:

(a) providing a substrate comprising a laterally extending surface having a plurality of spaced apart, electrically conductive features formed thereon, said plurality of features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features;
(b) forming a first, blanket layer of a low dielectric constant (“low k”) material over said substrate surface, said blanket layer filling the spaces between adjacent features and covering said features, the thickness of said blanket layer varying over said laterally extending surface and including thinner, recessed portions in the relatively wide spaces between adjacent features and thicker, non-recessed portions;
(c) selectively forming a layer of an etch-resistant mask material over the thinner, recessed portions of said blanket layer;
(d) selectively etching the thicker, non-recessed portions of said blanket layer of first, low k material exposed by said layer of mask material to substantially planarize the surface thereof;
(e) removing the layer of etch-resistant mask material;
(f) successively forming a relatively thinner layer of a second, oxide-based dielectric material and a relatively thicker layer of a third, low k material on the planarized surface of said layer of first, low k material;
and
(g) forming at least one via extending through said second and third dielectric material layers by an etching process.

5 more elements

A method of manufacturing a semiconductor device comprising a multi-layer metallization system having reduced variation of vertical capacitance, which method comprises the sequential steps of:

(a) providing a silicon wafer substrate having a laterally extending major surface with a dielectric layer formed thereon, with a plurality of spaced-apart, electrically conductive features formed in or on a surface of said dielectric layer for providing electrical contact areas, interlevel metallization, and/or interconnection routing of at least one active device region or component formed on or within said wafer substrate, said plurality of conductive features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features;
(b) forming a blanket layer of a first, low k material filling the spaces between adjacent features and covering said features, the thickness of said blanket layer varying over the laterally extending surface of said wafer substrate and including thinner, recessed portions in the relatively wide spaces between adjacent features and non-recessed portions;
(c) selectively forming a layer of an etch-resistant mask material over said recessed portions of said blanket layer;
(d) selectively etching said thicker, non-recessed portions of said blanket layer of first low k material, thereby substantially planarizing the surface thereof;
(e) removing said layer of etch-resistant mask material;
(f) successively forming a relatively thinner layer of a second, oxide-based dielectric material and a relatively thicker layer of a third, tow k material on said planarized surface of said layer of first, low k material;
(g) forming at feast one via extending through said second and third dielectric layers by means of an etching process wherein said layer of third, low k material is etched at a substantially greater rate than said layer of second dielectric material, thereby preventing or substantially reducing, over-etching of sail at least one via;
and
(h) filling said at least one via with a plug of an electrically conductive material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/640,080Filed 17 Aug 2000 · us provisional application
Priority: 18 Aug 1999
Granted: 9 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts
H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/092
Of dielectric parts thereof: by smoothing the dielectric parts
H10W 20/48
Characterised by their insulating parts: insulating materials thereof