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US 6,660,603 B2Granted
Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
AssigneeTexas Instruments Incorporated
InventorJozef Czeslaw Mitros
Life of this patent
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Abstract
An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90) is formed in the source extension region 50 and a transistor drain region 92 is formed between two drain alignment structures (74), (76) in the drain extension region (52).
Claims12
A method for forming a drain extension transistor, comprising:
- providing a semiconductor substrate with a plurality of isolation structures and a first well region of a first conductivity type;
- forming a masking layer on a first area of said first well region;
- implanting said first well region to form regions of a second conductivity type in said first well region adjacent to said masking layer;
- removing said masking region;
- forming a gate dielectric on said first well region;
- forming a gate layer on said gate dielectric;
- patterning said gate layer to form a gate structure and drain alignment structures such that said gate structure overlies a portion of said first well region and a portion of said regions of said second conductivity type;
- forming a patterned film to mask an area between said gate structure and said drain alignment structures;
- and
- simultaneously forming a source region and a drain region in said regions of said second conductivity type.
7 more elements
A method for forming a drain extension transistor, comprising:
- providing a semiconductor substrate with a plurality of isolation structures and a first well region of a first conductivity type;
- forming a masking layer on a first area of said first well region;
- implanting said first well region to form regions of a second conductivity type in said first well region adjacent to said masking layer;
- removing said masking region;
- forming a gate dielectric on said first well region;
- forming a gate layer on said gate dielectric;
- patterning said gate layer to form a gate structure such that said gate structure overlies a portion of said first well region and a portion of said regions of said second conductivity type and a portion of at least one of said isolation structures;
- and
- simultaneously forming a source region and a drain region in said regions of said second conductivity type.
6 more elements
Dependencies are inferred from the claim text.