Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors

A method of forming integrated circuitry comprising:

• forming a transistor gate line of undoped semiconductive material over a semiconductive substrate;
• subsequent to forming the transistor gate line, forming a layer comprising semiconductive material laterally proximate the transistor gate line, the layer joining with semiconductive material of the substrate laterally proximate the gate line and the layer comprising elevated source/drain material for a transistor of the gate line;
• removing elevated source/drain material portions to define elevated source/drain regions over the semiconductive substrate;
• and
• in a common step, providing conductivity enhancing impurity into both the elevated source/drain material and the gate line.

A method of forming integrated circuitry comprising:

• forming a pair of spaced apart gate lines in a first forming, the gate lines comprising semiconductive material over a semiconductive substrate;
• forming a layer comprising semiconductive material laterally proximate the gate lines in a second forming subsequent the first forming, the layer joining with semiconductive material of the substrate laterally proximate the gate lines and comprising elevated source/drain material for transistors of the gate lines;
• removing portions of the layer comprising semiconductive material to define elevated source/drain regions over the semiconductive substrate;
• commonly doping both the layer and the semiconductive material of the gate lines with a first dose of impurity provided at a first energy level;
• and
• commonly doping both the layer and the semiconductive material of the gate lines with a second dose of impurity provided at a second energy level.

A method of forming integrated circuitry comprising:

• forming a transistor gate line over a substrate;
• forming a layer comprising undoped semiconductive material laterally proximate the transistor gate line and over substrate areas corresponding to source/drain diffusion regions of the gate line, the semiconductive material layer joining with the substrate areas and comprising elevated source/drain material for the gate line;
• forming a patterned masking layer over the substrate and defining a masking layer opening thereover, the masking layer opening being disposed over only a portion of the undoped semiconductive material layer, the gate line having a semiconductive outer surface that is exposed through the masking layer opening;
• providing conductivity-modifying impurity through the masking layer opening and into both the elevated source/drain material and the exposed gate line outer surface;
• and
• after the providing of the conductivity-modifying impurity, selectively removing portions of semiconductive layer material to form elevated source/drain regions over the substrate areas.

A method of forming integrated circuitry comprising:

• forming semiconductive material over a substrate, wherein the forming of semiconductive material comprises:
• first forming semiconductive gate line material;
• and
• separately forming semiconductive elevated source/drain region material, the semiconductive material comprising material of a laterally proximate elevated source/drain region;
• and
• patterning the separately formed semiconductor material to define the laterally proximate elevated source/drain region over the substrate;
• and
• contemporaneously doping the semiconductive material of both the transistor gate line and the laterally proximate elevated source/drain region with a conductivity-modifying impurity.

A method of forming integrated circuitry comprising:

• first forming a transistor gate line of semiconductive material over a semiconductive substrate;
• second forming semiconductive material over the substrate laterally proximate the transistor gate line and comprising elevated source/drain material, the second forming subsequent the first forming;
• patterning and etching the elevated source/drain material into source/drain regions over the semiconductive substrate;
• providing conductivity-enhancing impurity into semiconductive material proximate the gate line to form source/drain regions;
• and
• after the providing, forming a refractory metal silicide cap over and in electrical connection with the semiconductive material of the transistor gate line.

A method of forming integrated circuitry comprising:

• forming semiconductive material over a substrate, the semiconductive material comprising separately formed material of both a transistor gate line and a laterally proximate elevated source/drain region, wherein the separately formed material of the elevated source drain region is patterned and etched to define such region over the semiconductive substrate;
• forming a common refractory metal layer over semiconductive material of the transistor gate line and semiconductive material of the elevated source/drain region;
• and
• exposing the substrate to conditions effect to render the refractory metal into a silicide layer.

A method of forming elevated source/drain regions of a field effect transistor comprising:

• forming semiconductive material laterally proximate a previously formed transistor gate;
• masking the semiconductive material to form covered portions and exposed portions, the exposed portions comprising elevated source/drain regions for the field effect transistor being formed;
• doping the exposed portions with a conductivity-enhancing impurity;
• stripping the masking after the doping;
• and
• selectively wet etching undoped portions of the semiconductive material relative to doped portions of the semiconductive material after the stripping, the selective etching defining the elevated source/drain regions laterally proximate the transistor gate.

A method of forming field effect transistors comprising:

• forming a layer of semiconductive material overlying and laterally proximate a plurality of transistor gates previously formed over a substrate;
• patterning and dry etching the semiconductive material to remove portions of the layer and to form elevated source/drain material laterally proximate the transistor gates;
• masking a first region of the elevated source/drain material while doping a second region of elevated source/drain material with conductivity-enhancing impurity of a second type;
• and
• masking the second region of the elevated source/drain material while doping the first region of elevated source/drain material with conductivity-enhancing impurity of a first type.