US 6,660,597 B2Granted

Method for manufacturing semiconductor integrated circuit device

AssigneeHitachi, Ltd.

InventorsRyoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto

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Abstract

In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Claims20

Dependent claims

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) preparing a silicon substrate having a first region and a second region on a principal surface;
(b) removing a film including a natural oxide film formed on the principal surface of the silicon substrate, and thereby exposing a silicon layer on the principal surface of the silicon substrate;
(c) forming, after the step (b), a first insulating film having a smaller relative dielectric constant than that of a silicon nitride film on the silicon layer;
(d) selectively removing the first insulating film in the second region, leaving the first insulating film in the first region, and thereby exposing the silicon layer in the second region;
(e) forming, after the step (d), a second insulating film having a larger relative dielectric constant than that of a silicon nitride film on the first insulating film in the first region and on the silicon layer in the second region;
(f) forming a first conductive layer on the second insulating film;
and
(g) patterning the first conductive layer, and thereby forming a gate electrode of a first MISFET comprised of the first conductive layer on the second insulating film in the first region and forming a gate electrode of a second MISFET comprised of the first conductive layer on the second insulating film in the second region,
wherein at least the steps (b) to (e) are continuously carried out without exposing the silicon substrate to air.

6 more elements

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) preparing a silicon substrate having a first region, a second region, a third region, and a fourth region on a principal surface;
(b) removing a film including a natural oxide film formed on the principal surface of the silicon substrate, and thereby exposing a silicon layer on the principal surface of the silicon substrate;
(c) forming, after the step (b), a first insulating film having a smaller relative dielectric constant than that of a silicon nitride film on the silicon layer;
(d) selectively removing the first insulating film in the third and fourth regions, leaving the first insulating film in the first and second regions, and thereby exposing the silicon layer in the third and fourth regions;
(e) forming, after the step (d), a second insulating film having a larger relative dielectric constant than that of a silicon nitride film on the first insulating film in the first and second regions, and on the silicon layer in the third and fourth regions;
(f) forming a first conductive layer of a first conductive type on the second insulating film in the first and third regions, and forming a second conductive layer of a second conductive type on the second insulating film in the second and fourth regions;
and
(g) patterning the first and second conductive layers, and thereby forming a gate electrode of a first MISFET comprised of the first conductive layer of the first conductive type on the second insulating film in the first region, forming a gate electrode of a second MISFET comprised of the second conductive layer of the second conductive type on the second insulating film in the second region, forming a gate electrode of a third MISFET comprised of the first conductive layer of the first conductive type on the second insulating film in the third region, and forming a gate electrode of a fourth MISFET comprised of the second conductive layer of the second conductive type on the second insulating film in the fourth region,
wherein at least the steps (b) to (e) are continuously carried out without exposing the silicon substrate to air.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/288,539Filed 6 Nov 2002
Priority: JP 2001-35063615 Nov 2001
Published: US 2003/0092233 A115 May 2003
Granted: 9 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 64/01342
On single crystalline silicon, e.g. chemical oxidation using a liquid: by deposition, e.g. evaporation, ALD or laser deposition
H10D 64/691
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates
H10D 84/0144
The components including insulated gates, e.g. IGFETs: manufacturing their gate insulating layers
H10D 84/0177
Manufacturing their gate conductors: the gate conductors having different materials or different implants