Double planar gated SOI MOSFET structure
AssigneeInternational Business Machines Corporation
InventorsJames W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson, Jed H. Rankin
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Abstract
A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
Claims9
A method for forming a double gated FET, comprising the steps of:
- forming on a substrate a first and a second line that comprises a channel region;
- etching areas within a semiconductor layer to form a source and a drain, wherein a side surface of the source and the drain contact opposing end surfaces of the first and second lines;
- and
- forming a gate disposed on a top surface and two side surfaces of the first and second lines and a top surface of the substrate;
- and
- wherein the second forming step comprises the steps of:
- filling areas surrounding the first and second lines and between the source and the drain with an oxide fill;
- etching a portion of the oxide fill to form an area that defines a gate, wherein the area that defines the gate is disposed between the source and the drain;
- and
- depositing a material to form a gate.
Dependencies are inferred from the claim text.