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US 6,660,588 B1Granted
High density floating gate flash memory and fabrication processes therefor
AssigneeAdvanced Micro Devices, Inc.
InventorsNian Yang, Zhigang Wang, Hyeon-seag Kim
Life of this patent
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Abstract
A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.
Claims49
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one;
- forming a reverse tunnel dielectric layer in the reduced trench;
- and
- filling the reduced trench with a floating gate material.
5 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one;
- and
- filling the reduced trench with a metal floating gate material.
4 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- depositing a barrier layer in the initial trench;
- and
- filling the reduced trench with a metal floating gate material.
4 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- forming a reverse tunnel dielectric layer in the reduced trench;
- reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lr1;
- and
- filling the reduced trench with a metal floating gate material.
5 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a bard mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench by forming sidewall/spacers to define a reduced trench having a first reduced lateral extent, Lr1;
- forming a reverse tunnel dielectric layer in the reduced trench;
- depositing a barrier layer in the reduced trench;
- and
- filling the reduced trench with a floating gate material.
6 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer, forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench by forming sidewall/spacers to define a reduced trench having a first reduced lateral extent, Lr1;
- forming second sidewalls, to reduce the first reduced lateral extent Lr1 to a second reduced lateral extent, Lr2;
- forming a reverse tunnel dielectric layer in the reduced trench;
- depositing a barrier layer in the reduced trench;
- and
- filling the reduced trench with a floating gate material.
6 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a had mask layer overlying the pad dielectric layer;
- forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench by forming sidewall/spacers to define a reduced trench having a first reduced lateral extent, Lr1;
- forming a reverse tunnel dielectric layer in the reduced trench, wherein the reverse tunnel dielectric layer comprises second sidewalls, to reduce the first reduced lateral extent Lr1 to a second reduced lateral extent, Lr2;
- depositing a barrier layer in the reduced trench;
- and
- filling the reduced trench wit a floating gate material.
6 more elements
A process for fabrication of a floating gate flash memory device comprising:
- providing a semiconductor substrate;
- forming a pad dielectric layer overlying the substrate;
- forming a hard mask layer overlying the pad dielectric layer;
- forming an initial trench through the bard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite bard mask sidewalls in the hard mask layer;
- reducing the initial lateral extent Li of the initial trench by forming sidewall/spacers to define a reduced trench having a first reduced lateral extent, Lr1;
- forming a reverse tunnel dielectric layer in the reduced trench, wherein the reverse tunnel dielectric layer comprises second sidewalls, to reduce the fist reduced lateral extent Lr1 to a second reduced lateral extent, Lr2;
- and
- filling the reduced trench with a floating gate material.
5 more elements
Dependencies are inferred from the claim text.