Method for forming a gate electrode in a semiconductor device

A method for forming a cell gate electrode in a non-volatile semiconductor device, the method comprising the steps of:

• i) forming a stacked structure of a tunnel oxide layer pattern, a first silicon layer pattern for a floating gate, and a nitride layer pattern on a semiconductor substrate;
• ii) forming a trench by etching the semiconductor substrate using the stacked structure as an etching mask;
• iii) forming a field oxide layer for burying the trench;
• iv) sequentially forming a dielectric interlayer and a second silicon layer pattern for a control gate on the first silicon layer pattern;
• v) forming a preliminary cell gate electrode having a stacked structure of the tunnel oxide layer pattern, the first silicon layer pattern, an dielectric interlayer pattern, and the second silicon layer pattern by etching predetermined portions of the control gate and the dielectric interlayer;
• and
• vi) performing a re-oxidation process for forming an oxide layer on an outer surface of the preliminary cell gate electrode and the semiconductor substrate by supplying an oxygen gas and a chlorine-including gas onto the semiconductor substrate including the preliminary cell gate electrode while restraining a thickness of the tunnel oxide layer pattern and the dielectric interlayer pattern from being increased.