Zero power memory cell with improved data retention

A method for forming a three channel zero power memory cell including a p-channel transistor, an n-channel write transistor, and an n-channel sense transistor, comprising:

• (a) implanting a p-type impurity into a p-type substrate in which the n-channel sense transistor will be formed;
• (b) implanting an n-type impurity into an n-type well in the p-type substrate in which the p-channel transistor will be formed;
• (c) forming a mask to allow implants to occur to the p-channel transistor;
• (d) performing a series of n-type dopant implants into the p-type substrate where the p-channel transistor will be formed;
• (e) growing a high voltage gate oxide on the p-type substrate;
• (f) forming a mask to allow implants to occur to the n-channel write transistor, said mask blocking implants to said n-channel sense transistor;
• and
• (g) performing a series of p-type implants into the p-type substrate where the n-channel write transistor will be formed.

In a method for forming a memory cell having an NMOS write transistor and PMOS and NMOS sense transistors formed in a substrate, an improvement comprising:

• masking the substrate at areas where the NMOS write transistor and PMOS sense transistor are formed;
• implanting a p-type impurity into the substrate at a channel area of the NMOS sense transistor;
• masking the substrate at areas where the NMOS write transistor and NMOS sense transistor are formed;
• implanting an n-type impurity into the substrate at a channel area of the PMOS sense transistor;
• masking the substrate at areas where the NMOS sense transistor and PMOS sense transistor are formed;
• and
• implanting a p-type impurity into the substrate at a channel area of the NMOS write transistor.