Method of forming conductive patterns formed in semiconductor integrated circuit device using multilayer interconnection
AssigneeOki Electric Industry Co., Ltd.
InventorMasahiko Utsunomiya
Life of this patent
Estimating the term…
Abstract
A method of forming conductive patterns comprises preparing layout data about macro cells, preparing data about layouts of top-layer conductive pattern metal cells and preparing data about conductive patterns between the macro cells, inputting to the macro cells and outputting from the macro cells. Then measurement-required points of the conductive patterns lying between the macro cells are specified. The top-layer conductive pattern metal cell is interposed in each of the measurement-required points. Finally, layouts of the macro cells and conductive patterns are determined so that layout data is created.
Claims21
A method of forming conductive patterns employed in a semiconductor integrated circuit device, comprising:
- preparing layout data about a plurality of macro cells;
- preparing data about layouts of top-layer conductive pattern metal cells;
- preparing data about conductive patterns between the macro cells, inputting to the macro cells and outputting from the macro cells;
- specifying measurement-required points of the conductive patterns lying between the macro cells;
- interposing the top-layer conductive pattern metal cell in each of the measurement-required points;
- and
- thereafter determining layouts of the macro cells and conductive patterns and thereby creating layout data.
A method of manufacturing a semiconductor integrated circuit device, comprising:
- preparing layout data about a plurality of macro cells;
- preparing data about layouts of top-layer wiring metal cells;
- preparing data about conductive patterns between the macro cells, inputting to the macro cells and outputting from the macro cells;
- specifying measurement-required points of the conductive patterns lying between the macro cells;
- interposing the top-layer conductive pattern metal cell in each of the measurement-required points;
- thereafter determining layouts of the macro cells and conductive patterns and thereby creating layout data;
- and
- manufacturing the semiconductor integrated circuit device, based on the layout data.
A method of forming conductive patterns employed in a semiconductor integrated circuit device, comprising:
- determining a plurality of macro cells employed in the semiconductor integrated circuit device and conductive patterns placed between the macro cells inputting to the macro cells and outputting from the macro cells and thereby obtaining a tentative circuit diagram;
- specifying measurement-required points of the conductive patterns between the macro cells in the circuit diagram;
- interposing top-layer conductive pattern metal cells in the measurement-required points;
- preparing layout data about the macro cells and data about layouts of the top-layer conductive pattern metal cells;
- and
- thereafter determining layouts of the macro cells and conductive patterns and thereby creating layout data.
Dependencies are inferred from the claim text.