Dynamic graphics and/or video memory power reducing circuit and method
AssigneeATI International SRL
InventorsDavid E. Sinclair, Eric Young
Life of this patent
Estimating the term…
Abstract
An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.
Claims32
A dynamic graphics and/or video memory power consumption reducing circuit comprising:
- at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests in a graphics processing subsystem;
- and
- at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
A dynamic graphics and/or video memory power consumption method comprising the steps of:
- generating memory request indication data based on detection of graphics and/or video memory request activity in a graphics processing subsystem;
- and
- controlling power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
A dynamic graphics and/or video memory power consumption reducing circuit comprising:
- at least one memory request detector that generates memory request indication data based on detection of graphics and/or video memory requests, wherein the memory request detector detects a static display screen condition to facilitate reduced power consumption of graphics and/or video memory in a graphics processing subsystem;
- and
- at least one dynamic memory activity based power controller, operatively responsive to the memory request indication data, having control logic operative to control power consumption of the graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period, wherein the control logic includes a programmable timer that is updated during memory request inactivity and reset based on memory request activity.
A dynamic memory power consumption reducing circuit, comprising:
- a memory request detector operative to generate memory request indication data based on detection of frame buffer memory requests;
- and
- a dynamic memory based power controller, operatively responsive to the memory request indication data, to control power consumption of frame buffer memory during system active modes based on the memory request indication data within a predetermined time period.
A graphics and/or video memory power consumption reducing circuit, comprising:
- a memory request detector operative to generate request indication data based on detection of graphics and/or memory requests from at least one request engine;
- and
- a power controller, operative to power down the entire graphics and/or video memory based on whether graphics and/or video memory requests are detected within a predetermined time period.
Dependencies are inferred from the claim text.