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US 6,657,310 B2Granted
Top layers of metal for high performance IC's
AssigneeMagic Corporation
InventorMou-Shiung Lin
Life of this patent
Estimating the term…
Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Claims25
A semiconductor device structure comprising:
- a semiconductor substrate having semiconductor devices formed thereon;
- an interconnecting metallization structure comprising lower metal lines, formed over and connected to said devices;
- electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;
- a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;
- openings through said passivation layer, exposing said electrical contact points;
- and
- an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, connected to said interconnecting metallization structure, wherein said upper metal lines are substantially thicker than said lower metal lines.
4 more elements
A semiconductor device structure comprising:
- a semiconductor substrate having semiconductor devices formed thereon;
- an interconnecting metallization structure comprising lower metal lines, formed over and connected to said devices;
- electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;
- a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;
- openings through said passivation layer, exposing said electrical contact points;
- and
- an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, connected to said interconnecting metallization structure, wherein said upper metal lines are substantially wider than said lower metal lines.
4 more elements
A semiconductor device structure comprising:
- a semiconductor substrate having semiconductor devices formed thereon;
- an interconnecting metallization structure comprising lower metal lines in layers, separated by inorganic intermetal dielectric layers, formed over and connected to said devices;
- electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;
- a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;
- openings through said passivation layer, exposing said electrical contact points;
- and
- an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, separated by organic dielectric layers, connected to said interconnecting metallization structure, wherein said organic dielectric layers are thicker than said inorganic intermetal dielectric layers.
4 more elements
Dependencies are inferred from the claim text.