Transistor having variable width gate electrode and method of manufacturing the same

A method of manufacturing a transistor comprising:

• providing a substrate;
• forming a gate electrode on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
• forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;
• forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion;
• and
• forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask.

A method of manufacturing a transistor comprising:

• providing a substrate;
• forming a gate electrode on said substrate, said gate electrode having an upper portion and a lower portion, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
• forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;
• forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion;
• and
• forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask;
• wherein said forming the gate electrode comprises:
• forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;
• forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;
• forming a sacrificial spacer on a side wall of said oxide pattern;
• removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;
• forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;
• depositing a polysilicon layer on the whole surface of said substrate and said oxide layer;
• planarizing said polysilicon layer;
• and
• removing said sacrificial spacer and said oxide layer.

A method of manufacturing a transistor comprising:

• forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;
• forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;
• forming a sacrificial spacer on a side wall of said oxide pattern;
• removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;
• forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;
• forming a polysilicon layer by depositing polysilicon on a whole surface of said substrate;
• planarizing said polysilicon layer;
• forming a gate electrode having an upper portion and a lower portion, by removing said sacrificial spacer and said oxide layer, wherein a horizontal width of the upper portion is greater than a horizontal width of a lower portion;
• doping a first impurity in said substrate at an angle which is offset from a direction perpendicular to a surface of the substrate, using said gate electrode as a mask;
• and
• doping a second impurity in said substrate having a higher concentration than that of the first impurity, at an angle which is coincident with the direction perpendicular to the surface of the substrate, using said gate electrode as a mask.