Radiation hardened semiconductor memory
AssigneeSTMicrocelectronics, Inc.
InventorTsiu C. Chan
Life of this patent
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Abstract
A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.
Claims10
A method for making a radiation hardened semiconductor memory cell of a semiconductor memory formed on a substrate, the memory cell having data storage nodes selectively coupled to a respective sense node by a transfer gate disposed therebetween on the substrate, the method comprising forming active gate isolation structures over the substrate between the data storage nodes, and biasing gates of the active gate isolation structures to a first voltage to prevent a conduction channel from forming under the active gate isolation structures.
A method for making a semiconductor static random access memory cell array for a semiconductor memory, the method comprising:
- forming a static memory cell having first and second pull-up transistors, each having a source region coupled to a first voltage and further having a drain region and a gate, first and second pull-down transistors, each having a source region coupled to a second voltage and further having a drain region and a gate, and first and second transfer transistors coupled between the drain regions the first and second pull-down transistors and first and second sense nodes, respectively, each transfer transistor having a transfer gate disposed between the respective drain region and sense node;
- and
- forming active gate isolation structures on the substrate disposed in between the drain regions of the first and second pull-down transistors, the active gate isolation structures biased to the second voltage to prevent a conduction channel from forming under the active gate isolation structures.
Dependencies are inferred from the claim text.