Method of fabricating a ferroelectric stacked memory cell

A process for forming a memory array, comprising:

• forming a first stacked cell by forming a first transistor in a first active region of a semiconductive substrate and forming a first capacitor above the first active region, the first capacitor having a first and a second plate separated by a first dielectric region;
• forming a second stacked cell by forming a second transistor in a second active region of the substrate and forming a second capacitor above the second active region, the second capacitor having a first and a second plate separated by a second dielectric region that is continuous with the first dielectric region;
• and
• forming a third capacitor having a first and a second plate separated from each other by a third dielectric region that is continuous with the first and second dielectric regions, the first and second capacitors being positioned in a first directional line that is transverse to a second directional line in which the second and third capacitors are positioned.

A process for making a memory array, comprising:

• forming a stacked first cell by forming a first transistor first active transition of the substrate and forming a first capacitor above the first active region, the first capacitor having a first and a second plate separated by a first dielectric region;
• forming a stacked second cell by forming a second transistor in a second active region of the substrate and forming a second capacitor above the second active region, the second capacitor having a first and a second plate separated by a second dielectric region that is continuous with the first dielectric region;
• forming a plurality of plate lines, wherein the second plate of each capacitor is connected to a respective plate line of the plurality of plate lines;
• shaping the first and second dielectric regions together as an elongated band extending in parallel to the respective plate lines;
• and
• forming a bit line connected to a conduction region of one of the first and second cells and positioned above the first and second capacitors, wherein the second plates of the first and second capacitors are formed of two bands of conductive material defining respective plate lines and running at a mutual distance above the first and second dielectric regions.

A process for making a memory array, comprising:

• forming a stacked first cell by forming a first transistor in a first active region of the substrate and forming a first capacitor above the first active region, the first capacitor having a first and a second plate separated by a first dielectric region;
• forming a stacked second cell by forming a second transistor in a second active region of the substrate and forming a second capacitor above the second active region, the second capacitor having a first and a second plate separated by a second dielectric region that is continuous with the first dielectric region;
• forming a plurality of plate lines, wherein the second plate of each capacitor is connected to a respective plate line of the plurality of plate lines;
• shaping the first and second dielectric regions together as an elongated band extending in parallel to the respective plate lines;
• and
• forming a bit line connected to a conduction region of one of the first and second cells and positioned above the first and second capacitors, wherein forming the first and second capacitors comprises laying a first layer of conductive material;
• defining said first layer of conductive material to form said first plates of said capacitors;
• making a layer of dielectric material above said first plates;
• making a second layer of conductive material above said layer of dielectric material;
• defining said second layer of conductive material to form said second plates of said capacitors;
• and defining said layer of dielectric material to form said continuous first and second dielectric regions.

A process for making a memory array, comprising:

• forming a stacked first cell by forming a first transistor in a first active region of the substrate and forming a first capacitor above the first active region, the first capacitor having a first and a second plate separated by a first dielectric region;
• forming a stacked second cell by forming a second transistor in a second active region of the substrate and forming a second capacitor above the second active region, the second capacitor having a first and a second plate separated by a second dielectric region that is continuous with the first dielectric region;
• forming a plurality of plate lines, wherein the second plate of each capacitor is connected to a respective plate line of the plurality of plate lines;
• shaping the first and second dielectric regions together as an elongated band extending in parallel to the respective plate lines;
• and
• forming a bit line connected to a conduction region of one of the first and second cells and positioned above the first and second capacitors, wherein the second plate of the first cell and the second plate of the second cell are discontinuous and parallel to one another.