Method for producing FET with source/drain region occupies a reduced area
AssigneeSharp Kabushiki Kaisha
InventorsHiroshi Iwata, Seizo Kakimoto, Masayuki Nakano, Kouichiro Adachi
Life of this patent
Estimating the term…
Abstract
A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
Claims3
A method for producing a semiconductor device comprising a device separation region and an active region, the method comprising the steps of:
- forming the device separation region on a silicon substrate from a material which substantially withstands silicon etching;
- sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film;
- coating a polycrystalline silicon film having a thickness which is larger than a distance between the gate electrode and the device separation region along a direction perpendicular to a longitudinal direction of the gate electrode;
- and
- performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed.
A method for producing a semiconductor device comprising the steps of:
- forming a device separation region on a silicon substrate from a material which substantially withstands silicon etching;
- sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film;
- coating a polycrystalline silicon film;
- performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed;
- and
- removing a portion of the polycrystalline silicon film, the polycrystalline silicon film having been formed on a lateral wall of the gate electrode with the gate electrode lateral wall insulation film being interposed between the polycrystalline silicon film and the lateral wall of the gate electrode.
Dependencies are inferred from the claim text.