MIM process for logic-based embedded RAM having front end manufacturing operation

A method for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device, said method comprising the steps of:

• providing a substrate;
• forming at least one transistor, an interlayer dielectric, at least one contact and at least one first metal layer on said substrate during a front end manufacturing operation of said capacitor on said substrate;
• thereafter depositing an inter-metal dielectric layer upon said substrate;
• thereafter performing a chemical mechanical polishing operation;
• thereafter performing a patterning operation;
• thereafter forming at least one plug upon said substrate and associated layers thereof;
• thereafter performing a lithographic operation upon said substrate;
• thereafter forming a plug upon said substrate and associated layers thereof;
• thereafter performing an etch back operation upon said substrate and associated layers thereof
• thereafter forming at least one dielectric deposition layer on said substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on said substrate;
• and
• thereafter forming at least one second metal layer on said substrate and associated layers thereof, thereby resulting in the formation of an MIM capacitor fully compatible with embedded DRAM logic devices and processes thereof, while alleviating process incompatibility, such that said MIM capacitor that may be efficiently integrated with associated DRAM logic devices utilizing at least one W-plug of said at least one metal two layer formed upon said substrate.