MIM process for logic-based embedded RAM

A method for forming a metal-interlayer-metal (MIM) device in an embedded memory device, said method comprising the steps of:

• providing a semiconductor substrate;
• forming at least one transistor during a front-end-of-line (FEOL) semiconductor fabrication operation upon said semiconductor substrate;
• thereafter forming a first inter-dielectric layer;
• subsequently forming an SiON layer followed thereafter by a second inter-dielectric layer;
• forming at least one High Aspect Ration (HAR) contact;
• thereafter depositing an SiON layer;
• performing a DRAM crown lithography operation;
• and thereafter initiating an oxide etch with a subsequent stop on said SiON layer;
• performing a Tungsten-plug etch back operation;
• thereafter depositing TiN and a photo resist coating thereof;
• performing next a photo resist and etch back operation;
• thereafter depositing a TA2O5 (or BST), TiN and a Tungsten layer;
• performing next a Tungsten/TiN/TA2O5 (or BST) etch back followed by a stop on an SiON layer, followed by the removal of said SiON layer;
• and
• thereafter implementing a BEOL process to finalize a fabrication of said MIM device in association with embedded memory device to thereby form an MIM device upon said semiconductor substrate utilizing no more than one additional photo mask layer prior to an implementation of a back-end-of-line (BEOL) semiconductor fabrication operation, wherein said MIM device comprises a low temperature MIM device that is fully compatible with logical semiconductor devices, thereby reducing associated manufacturing costs.

A method for forming a metal-interlayer-metal (MIM) device in an embedded memory device, said method comprising the steps of:

• providing a semiconductor substrate;
• depositing a photo resist coating upon said semiconductor substrate;
• performing a photo resist and TiN etch back operation to form at least one recess in a cell node thereof;
• thereafter stripping said photo resist coating;
• depositing subsequent TA2O5 (or BST), TiN and Tungsten deposition layers;
• performing a CMP operation upon a Tungsten deposition layer;
• stopping on an oxide layer thereof;
• performing a VIA1 photo and etch operation;
• thereafter forming at least one Tungsten-plug;
• thereafter forming at least one metal-2 layer;
• and
• thereafter implementing a BEOL process to finalize a fabrication of said MIM device in association with embedded memory device to thereby form an MIM device upon said semiconductor substrate utilizing no more than one additional photo mask layer prior to an implementation of a back-end-of-line (BEOL) semiconductor fabrication operation, wherein said MIM device comprises a low temperature MIM device that is fully compatible with logical semiconductor devices, thereby reducing associated manufacturing costs.