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US 6,656,782 B2Granted
Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor
AssigneeSTMicroelectronics S.r.l.
InventorsThomas Skotnicki, Stéphane Monfray, Alexandre Villaret
Life of this patent
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Abstract
The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.
Claims19
A process for fabricating an isolated-gate transistor comprising:
- forming a multilayer on a surface of a substrate bounded by a lateral isolation region of a shallow trench type, the multilayer comprising a first layer comprising a silicon-germanium alloy, and a second layer comprising silicon on the first layer;
- forming a gate oxide layer on the second layer;
- forming a gate on the gate oxide layer and on the lateral isolation region;
- removing the first layer for forming a tunnel under the second layer;
- filling the tunnel with an insulating material so that the transistor is isolated vertically from the substrate;
- and
- forming source and drain regions in the second layer.
4 more elements
A process for fabricating an isolated-gate transistor comprising:
- forming a multilayer on a surface of a substrate bounded by a lateral isolation region of a shallow trench type, the multilayer comprising a first layer and a second layer on the first layer;
- forming a gate oxide layer on the second layer;
- forming a gate on the gate oxide layer and on the lateral isolation region;
- removing the first layer for forming a tunnel under the second layer;
- filling the tunnel with an insulating material so that the transistor is isolated vertically from the substrate;
- and
- forming source and drain regions in the second layer after the tunnel has been filled with the insulating material.
4 more elements
A process for fabricating an isolated-gate transistor comprising:
- forming a multilayer on a surface of a substrate bounded by a lateral isolation region of a shallow trench type, the multilayer comprising a first layer and a second layer on the first layer;
- forming a gate oxide layer on the second layer;
- forming a gate on the gate oxide layer and on the lateral isolation region;
- forming source and drain regions in the second layer;
- removing the first layer for forming a tunnel under the second layer;
- and
- filling the tunnel with an insulating material so that the transistor is isolated vertically from the substrate, the tunnel being filled after the source and drain regions have been formed in the second layer.
4 more elements
Dependencies are inferred from the claim text.