US 6,656,764 B1Granted

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsMing-Fang Wang, Chien-Hao Chen, Liang-Gi Yao, Shih-Chang Chen

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Abstract

A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Claims29

Dependent claims

A method of forming a metal oxide semiconductor field effect transistor (MOSFET) device, with a gate insulator layer comprised of a high dielectric constant (high k), dielectric layer, on a semiconductor substrate, comprising the steps of:

forming a well region in a top portion of said semiconductor substrate,
forming a hard mask on a portion of top surface of said semiconductor substrate;
performing a first dry etch procedure to remove a top portion of said semiconductor substrate not covered by said hard mask, resulting in recessed regions in said semiconductor substrate, and a non-recessed portion of said semiconductor substrate covered by said hard mask;
forming a heavily doped source/drain region in a top portion of said recessed regions;
depositing a polysilicon layer;
performing a second dry etch procedure to form lightly doped source/drain (LDD), polysilicon spacers on the sides of said non-recessed portion of said semiconductor substrate;
forming a metal silicide region in a top portion of said heavily doped source/drain region;
forming a planarized first insulator layer, exposing top surface of said hard mask;
removing said hard mask resulting in space located between LDD polysilicon spacers, exposing top surface of underlying said non-recessed portion of said semiconductor substrate;
forming said gate insulator layer, comprised of said high k dielectric layer, in said space;
and
forming a conductive metal structure on said gate insulator layer.

9 more elements

A method of fabricating a complementary metal oxide semiconductor (CMOS) device on a semiconductor substrate, comprised of a P channel metal oxide semiconductor (PMOS), device, and of an N channel metal oxide semiconductor (NMOS), device, and featuring a gate insulator layer comprised of a high k metal oxide layer formed after completion of high temperature process steps, comprising the steps of:

providing a PMOS region in a first area of said semiconductor substrate to be used for said PMOS device, and providing an NMOS region in a second area of said semiconductor substrate to be used for said NMOS device;
forming an N well region in a top portion of said PMOS region;
forming a P well region in a top portion of said N well region;
depositing a silicon nitride layer;
performing a first anisotropic RIE procedure to define a silicon nitride shape, and to recess a top portion of said semiconductor substrate, in said PMOS and in said NMOS regions, resulting in a non-recessed portion of said semiconductor substrate, overlaid by said silicon nitride shape, in said PMOS region and in said NMOS regions;
performing a first ion implantation procedure to form a P type heavily doped source/drain region in a first recessed region located in said PMOS region;
performing a second ion implantation procedure to form an N type heavily doped source/drain region in a second recessed region located in said NMOS region;
depositing a first silicon oxide layer;
removing portion of said first silicon oxide layer located in said PMOS region;
depositing a P type, in situ doped polysilicon layer;
depositing a second silicon oxide layer;
removing portion of said second silicon oxide layer, portion of said P type, in situ doped polysilicon layer, and portion of said first silicon oxide layer located in said NMOS region;
depositing an N type, in situ doped polysilicon layer;
removing portion of said N type, in situ doped polysilicon layer and portion of said second silicon oxide layer located in said PMOS region, resulting in a remaining portion of said P type, in situ doped polysilicon layer in said PMOS region, and resulting in a remaining portion of said N type, in situ doped polysilicon layer located in said NMOS region;
performing a second anisotropic RIE procedure to form P type polysilicon, lightly doped source/drain (LDD), spacers on the sides of non-recessed portion of said semiconductor substrate and on the sides of a bottom portion of said silicon nitride shape, in said PMOS region, and to form N type polysilicon, LDD spacers on the sides of non-recessed portion of said semiconductor substrate and on the sides of a bottom portion of said silicon nitride shape, in said NMOS region;
depositing a first metal layer;
performing a patterning procedure to define metal shapes on the top surface of said P type heavily doped source/drain region, and on the top surface of said N type heavily doped source/drain region;
performing an anneal procedure to form metal silicide regions in said P type heavily doped source/drain region, and in said N type heavily doped source/drain region;
depositing a first insulator layer;
performing a chemical mechanical polishing procedure planarizing top surface of said first insulator layer and exposing the top surface of the silicon nitride shapes;
removing said silicon nitride shapes resulting in spaces located between polysilicon LDD spacers, exposing the top surfaces of the recessed portions of said semiconductor substrate;
depositing said high k metal oxide layer, completely filling said spaces;
depositing a second metal layer;
performing a third anisotropic RIE procedure to define metal gate structures, and to define gate insulator shape, comprised of said high k metal oxide layer;
depositing a second insulator layer;
forming contact hole openings in a second insulator layer and in said first insulator layer, exposing portions of top surfaces of said P type heavily doped source/drain region, of said N type heavily doped source/drain region, and of said metal gate structures;
and
forming metal contact structures in said contact hole openings.

25 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/146,287Filed 15 May 2002
Granted: 2 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers