Method of manufacturing a chip size package
AssigneeSanyo Electric Co., Ltd.
InventorsHiroyuki Shinogi, Ryoji Tokushige, Nobuyuki Takai
Life of this patent
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AssigneeSanyo Electric Co., Ltd.
InventorsHiroyuki Shinogi, Ryoji Tokushige, Nobuyuki Takai
Estimating the term…
First, a passivation film 3 having an opening K from which a part of the Al electrode 1 formed through an interlayer insulating film 2 made of a BPSG film is exposed is formed on a wafer. A wiring layer 7, which is connected to the Al electrode 1 exposed from the opening K and extended to the upper surface of the wafer, is formed. After a metal post 8 is formed on the wiring layer 7, a first groove TC1, which is located on the periphery of the chip inclusive of the wiring layer 7 and half cuts the wafer, is formed. The upper portion of the interlayer insulating film 2 is isotropically etched through the first groove TC1 to form a second groove TC2 having a larger opening diameter than that of the first groove TC1. The wafer surface inclusive of the wiring layer 7, second groove TC2 and first groove TC1 is resin-sealed to form an insulating resin layer R. Thereafter, a solder ball 12 is formed on the metal post 8 exposed from the insulating resin layer R. Finally, the wafer is fully cut through the insulating resin layer R formed in the first and the second grooves TC1 and TC2.
A method of manufacturing a semiconductor device comprising:
A method of manufacturing a semiconductor device comprising:
A method of manufacturing a semiconductor device comprising:
Dependencies are inferred from the claim text.