FeRAM capacitor post stack etch clean/repair
AssigneeTexas Instruments Incorporated
InventorsLindsey H. Hall, Scott R. Summerfelt
Life of this patent
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Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
Claims14
A method of performing a post capacitor stack etch clean for a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer over a substrate;
- etching the top electrode layer, the PZT ferroelectric layer, and the bottom electrode layer to form a capacitor stack, wherein the PZT ferroelectric layer has damage associated therewith due to the etching of the PZT ferroelectric layer;
- annealing the etched capacitor stack in a chamber having a lead source and oxygen, wherein a vapor pressure of the lead source is greater than a vapor pressure of the etched PZT ferroelectric layer, thereby facilitating a vapor transport of lead from the lead source to the etched PZT ferroelectric layer for repair thereof.
A method of performing a post capacitor stack etch treatment for a ferroelectric memory device, comprising:
- forming a bottom electrode diffusion barrier layer over a substrate;
- forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer in succession over the bottom electrode diffusion barrier layer;
- patterning a portion of the top electrode layer, the PZT ferroelectric layer and the bottom electrode layer in succession to form a capacitor stack overlying the bottom electrode diffusion barrier layer;
- repairing damage to the PZT ferroelectric layer due to the patterning of the capacitor stack, wherein the repairing comprises introducing lead into the PZT ferroelectric layer after the patterning thereof;
- and
- patterning a portion of the bottom electrode diffusion barrier layer which does not underlie the capacitor stack.
A method of performing a post capacitor stack etch treatment for a ferroelectric memory device, comprising:
- forming a bottom electrode diffusion barrier layer over a substrate;
- forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer in succession over the bottom electrode diffusion barrier layer;
- patterning a portion of the top electrode layer, the PZT ferroelectric layer and the bottom electrode layer in succession to form a capacitor stack overlying the bottom electrode diffusion barrier layer;
- introducing lead into the patterned PZT ferroelectric layer;
- and
- patterning a portion of the bottom electrode diffusion barrier layer which does not underlie the capacitor stack after formation of the capacitor stack.
Dependencies are inferred from the claim text.