Technique of monitoring abnormality in plurality of CPUs or controllers

A method of controlling an object with a plurality of controllers that are connected with one another and include a first controller and a second controller, said method comprising the steps of:

• (a) carrying out a first reset event, which resets a circuit configuration of a predetermined range including said second controller in response to input of a reset signal into said first controller;
• and
• (b) outputting the reset signal to said first controller when said second controller detects abnormality arising in said first controller,
• wherein said second controller does not output the reset signal to said first controller in response to the reset of said second controller in said step (a).

A method of detecting a processing error arising in any of at least two controllers included in a control system, each of said at least two controllers comprising an arithmetic logic operation unit that follows a specific program and carrying out predetermined processing according to the specific program, said method comprising the steps of:

• separating a first process from a second process, the first process causing a controller of interest, which executes the predetermined processing, to verify the validity of the predetermined processing based on a result of the predetermined processing, the second process causing another controller, which is different from said controller of interest, to verify the validity of the predetermined processing carried out by said controller of interest;
• carrying out the first process in which said controller of interest verifies the validity of the predetermined processing;
• and
• carrying out the second process in which said another controller receives the result of the predetermined processing carried out by said controller of interest and verifies the validity of the predetermined processing.

A control system comprising at least two controllers, each of said at least two controllers comprising an arithmetic logic operation unit that follows a specific program and carrying out predetermined processing according to the specific program,

• each of said at least two controllers comprising:
• a first verification unit that stores and carries out a first process, the first process causing a controller of interest, which executes the predetermined processing, to verify the validity of the predetermined processing based on a result of the predetermined processing;
• and
• a second verification unit that stores a second process and receives a result of the second process from another controller, which is different from said controller of interest, the second process causing said another controller to verify the validity of the predetermined processing carried out by said controller of interest.