Method, apparatus, and product for optimizing compiler with rotating register assignment to modulo scheduled code in SSA form

In a computer having one or more rotating registers and at least one memory unit having stored therein a first intermediate representation (first IR) of source code, a scheduler-assigner for allocating at least one of the one or more rotating registers, comprising:

• a software-pipelined instruction scheduler constructed and arranged to generate a first software-pipelined instruction schedule based on the first IR, the software-pipelined instruction scheduler is a modulo scheduler and the first software-pipelined instruction schedule is a modulo schedule;
• and
• a rotating register allocator constructed and arranged to designate a first live range of a loop-variant variable in the first software-pipelined instruction schedule as being allocated to a first rotating register, the rotating register allocator further is constructed and arranged to designate a second live range of a loop-variant variable in the first software-pipelined instruction schedule as being allocated to a second rotating register when available and, when not available, the software-pipelined instruction scheduler is further constructed and arranged to insert one or more spill code instructions in the first IR for the second live range, and to generate a second software-pipelined instruction schedule based on the first IR including the spill code instructions;
• wherein the first IR includes data flow information in SSA form.