Direct transformation of engineering change orders to synthesized IC chip designs
AssigneeLSI Logic Corporation
InventorsAndrey A. Nikitin, Andrej A. Zolotykh, Nikola Radovanovic
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Abstract
A change, such as an ECO, is transformed to a gate-level netlist. The change is incorporated in cells of a synthesizable source design. A domain is defined in the netlist that contains cells that are equivalent to the cells of the source design that incorporate the change. The cells of the synthesizable source design that incorporate the change are substituted for the domain in the netlist. The substituted synthesizable source design domain is resynthesized into the gate-level netlist that includes the change.
Claims21
A process of executing at least one change to a gate-level netlist comprising steps of:
- a) incorporating the at least one change to cells of a synthesizable source design;
- b) using logic cells incorporating the change to the synthesizable source design to define at least one domain of the netlist containing cells that are equivalent to the cells of the source design that incorporate the at least one change;
- c) substituting the cells of the source design that incorporate the at least one change for the domain;
- and
- d) resynthesizing the substituted cells into the gate-level netlist.
A process of altering a gate-level netlist with at least one change, wherein the netlist includes cells defining the circuit and wherein the at least one change is incorporated in a source design, the process comprising steps of:
- a) identifying all source design cells within the source affected by the at least one change;
- b) defining a first domain based on identified logic cells within the source design;
- c) identifying a second domain within the netlist containing synthesized design cells that are equivalent to the source design cells in the first domain;
- d) substituting the first domain for the second domain;
- and
- e) performing the changes on the substituted first domain.
A storage medium having stored therein processor executable instructions that enable a processor to apply at least one change to a gate-level netlist incorporated in cells of a synthesizable source design, the processor executable instructions including:
- first identifying instructions that enable the processor to identify all source design cells affected by the at least one change;
- domain defining instructions that enable the processor to define a first domain based on identified logic cells of the source design;
- second identifying instructions that enable the processor to identify a second domain within the netlist containing synthesized design cells that are equivalent to the source design cells in the first domain;
- substitution instructions that enable the processor to substitute the first domain for the second domain;
- and
- changing instructions that enable the processor to perform the changes on the substituted first domain.
A process of identifying a domain within a netlist containing synthesized design cells that are equivalent to cells in a domain of a source design comprising steps of:
- identifying synthesized design cells in the netlist that are equivalent to source design cells in the source design,
- identifying a border of the domain of the source design that comprises all source design cells and wires that are outside of the domain of the source design and are coupled to a logic cell in the domain of the source design, and
- selecting synthesized design cells that are equivalent to cells in at least the border.
Dependencies are inferred from the claim text.