US 6,651,238 B1 · Providing fault coverage of interconnect in an FPGA

Abstract

Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

Claims20

Dependent claims

A method of providing fault coverage for programmable interconnect in a programmable logic device, the method comprising:

identifying programmable interconnect and function generators used in a user's design;
generating a first derivative design by using the programmable interconnect in the user's design and replacing functions implemented in the function generators in the user's design with a first logic function;
providing a first vector to the first derivative design;
and
observing predetermined nodes in the first derivative design to identify a first type of fault in the programmable interconnect used in the user's design.

2 more elements

Dependencies are inferred from the claim text.

Providing fault coverage of interconnect in an FPGA

Life of this patent

Providing fault coverage of interconnect in an FPGA

Life of this patent

Abstract

Claims20